Xilong Xie

Orcid: 0009-0005-9988-2940

According to our database1, Xilong Xie authored at least 6 papers between 2023 and 2025.

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Bibliography

2025
DeepCEE: Efficient Cross-Region Model Distributed Training System under Heterogeneous GPUs and Networks.
CoRR, May, 2025

Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache.
J. Syst. Archit., 2025

FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

FuseFPS: Accelerating Farthest Point Sampling with Fusing KD-tree Construction for Point Clouds.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
ATA-Cache: Contention Mitigation for GPU Shared L1 Cache with Aggregated Tag Array.
CoRR, 2023


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