Xilong Xie

Orcid: 0009-0005-9988-2940

According to our database1, Xilong Xie authored at least 9 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Accelerating LLM Inference via Low-Bit Fine-Grained Quantization Algorithm and Bit-Level Accelerator Co-Design.
IEEE Trans. Computers, February, 2026

2025
DeepCEE: Efficient Cross-Region Model Distributed Training System under Heterogeneous GPUs and Networks.
CoRR, May, 2025

Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache.
J. Syst. Archit., 2025

Amove: Accelerating LLMs through Mitigating Outliers and Salient Points via Fine-Grained Grouped Vectorized Data Type.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

PointISA: ISA-Extensions for Efficient Point Cloud Analytics via Architecture and Algorithm Co-Design.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

FuseFPS: Accelerating Farthest Point Sampling with Fusing KD-tree Construction for Point Clouds.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
ATA-Cache: Contention Mitigation for GPU Shared L1 Cache with Aggregated Tag Array.
CoRR, 2023


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