Shaojun Wei

According to our database1, Shaojun Wei authored at least 211 papers between 2003 and 2019.

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Bibliography

2019
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distrib. Syst., 2019

Face Alignment With Expression- and Pose-Based Adaptive Initialization.
IEEE Trans. Multimedia, 2019

Reconfigurable Architecture for Neural Approximation in Multimedia Computing.
IEEE Trans. Circuits Syst. Video Techn., 2019

A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching.
IEEE Trans. Circuits Syst. Video Techn., 2019

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

An STT-MRAM Based in Memory Architecture for Low Power Integral Computing.
IEEE Trans. Computers, 2019

An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width.
J. Solid-State Circuits, 2019

A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Reliable Physical Unclonable Function Based on Differential Charging Capacitors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Constructing Concurrent Data Structures on FPGA with Channels.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Massive MIMO Detection Algorithm and VLSI Architecture
Springer, ISBN: 978-981-13-6361-0, 2019

2018
Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM.
IEEE Trans. VLSI Syst., 2018

Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems.
IEEE Trans. Signal Processing, 2018

Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays.
IEEE Trans. Parallel Distrib. Syst., 2018

Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration.
IEEE Trans. Parallel Distrib. Syst., 2018

A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128\times 8~64$ -QAM Massive MIMO in 65 nm CMOS.
IEEE Trans. on Circuits and Systems, 2018

A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT.
IEEE Trans. on Circuits and Systems, 2018

HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing.
IEEE Trans. on Circuits and Systems, 2018

Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.
J. Solid-State Circuits, 2018

Optimization of Softmax Layer in Deep Neural Network Using Integral Stochastic Computation.
J. Low Power Electronics, 2018

FP-BNN: Binarized neural network on FPGA.
Neurocomputing, 2018

Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution.
Computer Architecture Letters, 2018

Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis.
IEEE Access, 2018

A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Bit-width Adaptive Accelerator Design for Convolution Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Efficient Hardware Architecture of Softmax Layer in Deep Neural Network.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

An efficient kernel transformation architecture for binary- and ternary-weight neural network inference.
Proceedings of the 55th Annual Design Automation Conference, 2018

LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA.
Proceedings of the 55th Annual Design Automation Conference, 2018

A Full Multicast Reconfigurable Non-blocking Permutation Network.
Proceedings of the International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2018

A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

An Asynchronous Energy-Efficient CNN Accelerator with Reconfigurable Architecture.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.
IEEE Trans. VLSI Syst., 2017

Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture.
IEEE Trans. Signal Processing, 2017

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory.
IEEE Trans. Parallel Distrib. Syst., 2017

CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays.
IEEE Trans. Parallel Distrib. Syst., 2017

A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems.
IEEE Trans. Parallel Distrib. Syst., 2017

Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks.
IEEE Trans. Information Forensics and Security, 2017

PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC.
IEEE Trans. on Circuits and Systems, 2017

An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation.
IEEE Systems Journal, 2017

Implementation of in-loop filter for HEVC decoder on reconfigurable processor.
IET Image Processing, 2017

Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion.
IEEE Access, 2017

Multi-CNN and decision tree based driving behavior evaluation.
Proceedings of the Symposium on Applied Computing, 2017

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Memory fartitioning-based modulo scheduling for high-level synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM.
Proceedings of the 54th Annual Design Automation Conference, 2017

A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment.
Proceedings of the 54th Annual Design Automation Conference, 2017

A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications.
Proceedings of the 54th Annual Design Automation Conference, 2017

Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.
Proceedings of the 54th Annual Design Automation Conference, 2017

Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect.
Proceedings of the 54th Annual Design Automation Conference, 2017

Energy-aware loops mapping on multi-vdd CGRAs without performance degradation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Trigger-Centric Loop Mapping on CGRAs.
IEEE Trans. VLSI Syst., 2016

Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures.
IEEE Trans. VLSI Syst., 2016

CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache.
IEEE Trans. VLSI Syst., 2016

A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing.
IEEE Trans. VLSI Syst., 2016

Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures.
IEEE Trans. VLSI Syst., 2016

Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Parallel Distrib. Syst., 2016

TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions.
IEEE Trans. Parallel Distrib. Syst., 2016

Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture.
IEEE Trans. Information Forensics and Security, 2016

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator.
IEEE Trans. Circuits Syst. Video Techn., 2016

A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation.
IEEE Trans. on Circuits and Systems, 2016

Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations.
Microelectronics Journal, 2016

Temperature-aware multi-application mapping on network-on-chip based many-core systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform.
IEICE Transactions, 2016

A fast face detection architecture for auto-focus in smart-phones and digital cameras.
SCIENCE CHINA Information Sciences, 2016

A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration.
Computer Architecture Letters, 2016

Energy management on DVS based coarse-grained reconfigurable platform.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Temperature-aware task scheduling heuristics on Network-on-Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Multibank memory optimization for parallel data access in multiple data arrays.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels.
IEEE Trans. VLSI Syst., 2015

Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms.
IEEE Trans. VLSI Syst., 2015

Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures.
IEEE Trans. VLSI Syst., 2015

A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures.
IEEE Trans. VLSI Syst., 2015

A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks.
IEEE Trans. VLSI Syst., 2015

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm.
TRETS, 2015

Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding".
IEEE Trans. Multimedia, 2015

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding.
IEEE Trans. Multimedia, 2015

A real-time time-consistent 2D-to-3D video conversion system using color histogram.
IEEE Trans. Consumer Electronics, 2015

A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency.
IEEE Trans. on Circuits and Systems, 2015

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern Based Feature.
Sensors, 2015

A Novel 2D-to-3D Video Conversion Method Using Time-Coherent Depth Maps.
Sensors, 2015

High-Performance Motion Estimation for Image Sensors with Video Compression.
Sensors, 2015

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction.
Sensors, 2015

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array.
Journal of Circuits, Systems, and Computers, 2015

Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD.
IEICE Transactions, 2015

The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture.
IEICE Transactions, 2015

Battery-Aware Loop Nests Mapping for CGRAs.
IEICE Transactions, 2015

Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations.
IEICE Transactions, 2015

Exploring partitioning methods for multicast in 3D bufferless Network on Chip.
IEICE Electronic Express, 2015

Mapping of Embedded Applications on Hybrid Networks-on-Chip with Multiple Switching Mechanisms.
Embedded Systems Letters, 2015

Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints.
SCIENCE CHINA Information Sciences, 2015

A Multi-modal 2D + 3D Face Recognition Method with a Novel Local Feature Descriptor.
Proceedings of the 2015 IEEE Winter Conference on Applications of Computer Vision, 2015

Partitioning Methods for Multicast in Bufferless 3D Network on Chip.
Proceedings of the Computer Engineering and Technology - 19th CCF Conference, 2015

Neural approximating architecture targeting multiple application domains.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Real-time time-consistent 2D-to-3D video conversion based on color histogram.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Efficient lane detection system based on monocular camera.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

An automatic depth map generation method by image classification.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Acceleration of Nested Conditionals on CGRAs via Trigger Scheme.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Joint affine transformation and loop pipelining for mapping nested loop on CGRAs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

RNA: a reconfigurable architecture for hardware neural acceleration.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Acceleration of control flows on reconfigurable architecture with a composite method.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Efficient memory partitioning for parallel data access in multidimensional arrays.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Scheduling stream programs with improving arithmetic unit usage on NoC-based VLIW multi-core architectures.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Battery-aware mapping optimization of loop nests for CGRAs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time.
IEEE Trans. VLSI Syst., 2014

SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration.
IEEE Trans. VLSI Syst., 2014

Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method.
IEEE Trans. VLSI Syst., 2014

Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling.
IEEE Trans. VLSI Syst., 2014

A High-Utilization Scheduling Schemeof Stream Programs on ClusteredVLIW Stream Architectures.
IEEE Trans. Parallel Distrib. Syst., 2014

A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps.
Sensors, 2014

A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision.
J. Solid-State Circuits, 2014

Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors.
J. Parallel Distrib. Comput., 2014

MapReduce inspired loop mapping for coarse-grained reconfigurable architecture.
SCIENCE CHINA Information Sciences, 2014

Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture.
SCIENCE CHINA Information Sciences, 2014

Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system.
SCIENCE CHINA Information Sciences, 2014

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor.
SCIENCE CHINA Information Sciences, 2014

Optimization of speeded-up robust feature algorithm for hardware implementation.
SCIENCE CHINA Information Sciences, 2014

A fast and robust traffic sign recognition method using ring of RIBP histograms based feature.
Proceedings of the 2014 IEEE International Conference on Robotics and Biomimetics, 2014

A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A parallel hardware architecture for fast integral image computing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Map-reduce inspired loop parallelization on CGRA.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A FAST Extreme Illumination Robust Feature in Affine Space.
Proceedings of the 22nd International Conference on Pattern Recognition, 2014

Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Teach Reconfigurable Computing using mixed-grained fabrics based hardware infrastructure.
Proceedings of the IEEE Frontiers in Education Conference, 2014

Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Low-Power Reconfigurable Processor Utilizing Variable Dual VDD.
IEEE Trans. on Circuits and Systems, 2013

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration.
Journal of Systems Architecture - Embedded Systems Design, 2013

Energy-efficient stream task scheduling scheme for embedded multimedia applications on multi-issued stream architectures.
Journal of Systems Architecture - Embedded Systems Design, 2013

Calibration Techniques for Low-Power Wireless Multiband Transceiver.
IJDSN, 2013

Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features.
IEICE Transactions, 2013

Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture.
IEICE Transactions, 2013

Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs.
IEICE Transactions, 2013

The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture.
IEICE Transactions, 2013

Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System.
IEICE Transactions, 2013

Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip.
IEICE Transactions, 2013

An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video.
SCIENCE CHINA Information Sciences, 2013

Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.
SCIENCE CHINA Information Sciences, 2013

ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor.
SCIENCE CHINA Information Sciences, 2013

SPC: An Approach to Guarantee Performance in Cost Oriented Mapping Algorithm for NoC Architectures.
Proceedings of the IEEE Eighth International Conference on Networking, 2013

Battery-Aware MAC Analytical Modeling for Extending Lifetime of Low Duty-Cycled Wireless Sensor Network.
Proceedings of the IEEE Eighth International Conference on Networking, 2013

Compiler-assisted leakage energy optimization of media applications on stream architectures.
Proceedings of the International Symposium on Quality Electronic Design, 2013

An inductive-coupling interconnected application-specific 3D NoC design.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Affine transformations for communication and reconfiguration optimization of loops on CGRAs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Mapping IDCT of MPEG2 on Coarse-Grained Reconfigurable Array for Matching 1080p Video Decoding.
Proceedings of the Advanced Technologies, Embedded and Multimedia for Human-centric Computing, 2013

Polyhedral model based mapping optimization of loop nests for CGRAs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A power-efficient network-on-chip for multi-core stream processors.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture.
IEICE Transactions, 2012

Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC.
IEICE Transactions, 2012

Multi-Battery Scheduling for Battery-Powered DVS Systems.
IEICE Transactions, 2012

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture.
IEICE Transactions, 2012

Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Transactions, 2012

Reducing configuration contexts for coarse-grained reconfigurable architecture.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Low Power Schedule Algorithm for Embedded Multimedia Applications Basing on Imagine-L Processor.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

An Efficient Hardware Random Number Generator Based on the MT Method.
Proceedings of the 12th IEEE International Conference on Computer and Information Technology, 2012

2011
A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Performance evaluation modeling for reconfigurable processor.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

An energy efficiency task scheduling algorithm for streaming applications on multiprocessor SoC.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System.
IEICE Transactions, 2010

CropNET: A Wireless Multimedia Sensor Network for Agricultural Monitoring.
IEICE Transactions, 2010

Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System.
IEICE Transactions, 2010

A reconfigurable multi-processor SoC for media applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A VLSI design of sensor node for wireless image sensor network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Reconfigurable computing - evolution of Von Neumann architecture.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Battery aware tasks allocating algorithm for multi-battery operated system.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Mixed-level modeling for network on chip infrastructure in SoC design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Compiler Framework for Reconfigurable Computing Architecture.
IEICE Transactions, 2009

Buffer planning for application-specific networks-on-chip design.
Science in China Series F: Information Sciences, 2009

2008
Key technologies of system on chip design.
Science in China Series F: Information Sciences, 2008

2007
Battery-Aware Variable Voltage Scheduling on Real-Time Multiprocessor Platforms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
On handling the fixed-outline constraints of floorplanning using less flexibility first principles.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2003
Emerging markets: design goes global.
Proceedings of the 40th Design Automation Conference, 2003


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