Xuansheng Ji

According to our database, Xuansheng Ji authored at least 5 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Polar Phase-Tracking Receiver With Two-Point Injection Technique.

Xuansheng Ji, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

IEEE J. Solid State Circuits, May, 2025

An Ultra-Low-Voltage Bias-Current-Free Fractional-N Hybrid PLL With Voltage-Mode Phase Detection and Interpolation.

Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

IEEE J. Solid State Circuits, January, 2025

A 0.5V 0.55mm² Bias-Current-Free BLE Transceiver with 1-Bit Delay-Based Demodulation for Energy-Harvesting IoT applications.

Liqun Feng, Xuansheng Ji, Qianxian Liao, Longhao Kuang, Yunzhao Nie, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS.

Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction.

Jiahao Zhao, Xuansheng Ji, Su Han, Ziwei Wang, Woogeun Rhee, Zhihua Wang

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022