Y. V. Sai Dinesh

According to our database, Y. V. Sai Dinesh authored at least 4 papers between 2022 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Reconfigurable VLSI Design Architecture for Deep Learning Established Forelimb and Hindlimb Gesture Recognition for Rehabilitation Application.

Anagha Nimbekar, Y. V. Sai Dinesh, Arvind Gautam, Vidhumouli Hunsigida, Appa Rao Nali, Amit Acharyya

IEEE Access, 2023

Digital Twin Based Fault-Tolerance Framework for RRAM Based Neural Computing Systems.

Chandrasekhara Srinivas Vatti, Y. V. Sai Dinesh, Anagha Nimbekar, Amit Acharyya

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

Low Complexity Reconfigurable-Scalable Architecture Design Methodology for Deep Neural Network Inference Accelerator.

Anagha Nimbekar, Chandrasekhara Srinivas Vatti, Y. V. Sai Dinesh, Sunidhi Singh, Tarun Gupta, Ramesh Reddy Chandrapu, Amit Acharyya

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

VLSI Architecture Design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application.

Anagha Nimbekar, Y. V. Sai Dinesh, Arvind Gautam, Vidhumouli Hunsigida, Appa Rao Nali, Amit Acharyya

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022