Yair Linn

According to our database1, Yair Linn authored at least 12 papers between 2004 and 2014.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Efficient M-PSK lock detectors and SNR estimators.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

New structures for modulation classification and SNR estimation with applications to Cognitive Radio and Software Defined Radio.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2012
An Ultra Low Cost Wireless Communications Laboratory for Education and Research.
IEEE Trans. Educ., 2012

2009
Robust M-PSK phase detectors for carrier synchronization PLLs in coherent receivers: theory and simulations.
IEEE Trans. Commun., 2009

A Carrier-Independent Non-Data-Aided Real-Time SNR Estimator for M-PSK and D-MPSK Suitable for FPGAs and ASICs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2007
Efficient loop filter design in FPGAs for Phase Lock Loops in high-datarate wireless receivers - theory and case study.
Proceedings of the Wireless Telecommunications Symposium, 2007

2006
A self-normalizing symbol synchronization lock detector for QPSK and BPSK.
IEEE Trans. Wirel. Commun., 2006

An Optimal Adaptive M-PSK Carrier Phase Detector Suitable for Fixed-Point Hardware Implementation within FPGAs and ASICs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A Novel Method for Travel-Time Measurement for Geophysical Inversion Problems.
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2006

2004
A family of self-normalizing carrier lock detectors and E<sub>S</sub>/N<sub>0</sub> estimators for M-PSK and other phase Modulation schemes.
IEEE Trans. Wirel. Commun., 2004

Quantitative analysis of a new method for real-time generation of SNR estimates for digital phase modulation signals.
IEEE Trans. Wirel. Commun., 2004

A new NDA timing error detector for BPSK and QPSK with an efficient hardware implementation for ASIC-based and FPGA-based wireless receivers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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