Rajeevan Chandel

According to our database, Rajeevan Chandel authored at least 23 papers between 2007 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Proposal and analysis of carbon nanotube based differential multibit through glass vias.

Ajay Kumar, Rajeevan Chandel, Rohit Dhiman

Microelectron. J., 2022

Improving the Flare Perturbation Response of Gasket Monopole Antenna for Custom Frequency Solutions.

Deepanshu Kaushal, Rajeevan Chandel

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021

A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects.

Girish Kumar Mekala, Yash Agrawal, Vobulapuram Ramesh Kumar, Rajeevan Chandel

Microelectron. J., 2021

High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects.

Sunil Jadav, Shubham Tayal, Rajeevan Chandel, Munish Vashishath

Microelectron. J., 2021

Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects.

Ashish Singh, Rajeevan Chandel, Rohit Dhiman

Integr., 2021

Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS.

Neha Sharma, Rajeevan Chandel

Int. J. Model. Simul. Sci. Comput., 2021

2018

A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects.

Yash Agrawal, Girish Kumar Mekala, Rajeevan Chandel

Circuits Syst. Signal Process., 2018

2017

Modelling and performance analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects.

Girish Kumar Mekala, Yash Agrawal, Rajeevan Chandel

IET Circuits Devices Syst., 2017

Stability analysis of SRAM cell using CNT and GNR field effect transistors.

Parmjit Singh, Rajeevan Chandel, Neha Sharma

Proceedings of the Tenth International Conference on Contemporary Computing, 2017

2016

Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications.

Sanjay Singh Rajput, Ashish Singh, Ashwani Kumar Chandel, Rajeevan Chandel

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Performance Analysis of Top-Contact MLGNR Based Interconnects.

Ramesh Kumar, Rohit Dhiman, Rajeevan Chandel

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

2015

Dynamic Crosstalk Analysis in Coupled Interconnects for Ultra-Low Power Applications.

Rohit Dhiman, Rajeevan Chandel

Circuits Syst. Signal Process., 2015

Timing and Stability Analysis of Carbon Nanotube Interconnects.

Girish Kumar Mekala, Rajeevan Chandel, Yash Agrawal

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Performance Analysis of Multilayer Graphene Nano-Ribbon in Current-Mode Signaling Interconnect System.

Yash Agrawal, Rajeevan Chandel, Girish Kumar Mekala

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014

Carbon Nanotube Based Delay Model For High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique.

Sunil Jadav, Munish Vashistah, Rajeevan Chandel

CoRR, 2014

2012

Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications.

Rohit Dhiman, Rajeevan Chandel

J. Low Power Electron., 2012

Netlist bipartitioning using particle swarm optimisation technique.

Sandeep Singh Gill, Rajeevan Chandel, Ashwani Kumar Chandel

Int. J. Artif. Intell. Soft Comput., 2012

2011

Resistive analysis of mixed carbon nanotube bundle interconnect and its comparison with copper interconnect.

T. Alam, Rohit Dhiman, Rajeevan Chandel

Proceedings of the ICWET '11 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 25, 2011

2010

Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications.

Ashutosh Nandi, Rajeevan Chandel

J. Low Power Electron., 2010

Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique.

Kiran K. Chaddha, Rajeevan Chandel

J. Low Power Electron., 2010

Impact of skew and jitter on the performance of VLSI interconnects.

Gargi Khanna, Rajeevan Chandel, Ashwani Kumar Chandel

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2007

An analysis of interconnect delay minimization by low-voltage repeater insertion.

Rajeevan Chandel, Sankar Sarkar, Rajendra Prasad Agarwal

Microelectron. J., 2007

Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects.

Rajeevan Chandel, Sankar Sarkar, Ashwani Kumar Chandel

J. Low Power Electron., 2007