Rajeevan Chandel

According to our database1, Rajeevan Chandel authored at least 18 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects.
Microelectron. J., 2021

2018
A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects.
Circuits Syst. Signal Process., 2018

2017
Modelling and performance analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects.
IET Circuits Devices Syst., 2017

Stability analysis of SRAM cell using CNT and GNR field effect transistors.
Proceedings of the Tenth International Conference on Contemporary Computing, 2017

2016
Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Performance Analysis of Top-Contact MLGNR Based Interconnects.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

2015
Dynamic Crosstalk Analysis in Coupled Interconnects for Ultra-Low Power Applications.
Circuits Syst. Signal Process., 2015

Timing and Stability Analysis of Carbon Nanotube Interconnects.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Performance Analysis of Multilayer Graphene Nano-Ribbon in Current-Mode Signaling Interconnect System.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014
Carbon Nanotube Based Delay Model For High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique.
CoRR, 2014

2012
Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications.
J. Low Power Electron., 2012

Netlist bipartitioning using particle swarm optimisation technique.
Int. J. Artif. Intell. Soft Comput., 2012

2011
Resistive analysis of mixed carbon nanotube bundle interconnect and its comparison with copper interconnect.
Proceedings of the ICWET '11 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 25, 2011

2010
Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications.
J. Low Power Electron., 2010

Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique.
J. Low Power Electron., 2010

Impact of skew and jitter on the performance of VLSI interconnects.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2007
An analysis of interconnect delay minimization by low-voltage repeater insertion.
Microelectron. J., 2007

Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects.
J. Low Power Electron., 2007


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