Yasushi Terada

According to our database, Yasushi Terada authored at least 7 papers between 1988 and 1994.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1994

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.

Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

IEEE J. Solid State Circuits, April, 1994

1992

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories.

Yoshikazu Miyawaki, Takeshi Nakayama, Shin'ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

IEEE J. Solid State Circuits, April, 1992

1991

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller.

Takeshi Nakayama, Shin'ichi Kobayashi, Yoshikazu Miyawaki, Yasushi Terada, Natsuo Ajika, Makoto Ohi, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara, Kimio Suzuki

IEEE J. Solid State Circuits, November, 1991

1990

A high-speed parallel sensing architecture for multi-megabit flash E²PROMs.

Kiyoteru Kobayashi, Tatsuo Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara

IEEE J. Solid State Circuits, February, 1990

1989

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs.

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

IEEE J. Solid State Circuits, October, 1989

A 5 V only one-transistor 256 K EEPROM with page-mode erase.

Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

IEEE J. Solid State Circuits, August, 1989

1988

A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM.

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara

IEEE J. Solid State Circuits, February, 1988