Yawei Lu

Orcid: 0000-0002-1074-2855

According to our database1, Yawei Lu authored at least 14 papers between 2013 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
On the Effective Throughput of Coded Caching With Heterogeneous User Preferences: A Game Theoretic Perspective.
IEEE Trans. Commun., 2021

2020
User Preference Aware Lossless Data Compression at the Edge.
IEEE Trans. Commun., 2020

Latency-Minimized Design of secure transmissions in UAV-Aided Communications.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Computation-Aided Data Transmission for Remote Reconstruction of Trajectories of Dynamical Systems.
Proceedings of the IEEE Global Communications Conference, 2020

User Preference Aware Lossy Data Compression for Edge Caching.
Proceedings of the IEEE Global Communications Conference, 2020

2019
On the Effective Throughput of Coded Caching: A Game Theoretic Perspective.
CoRR, 2019

Coded Caching Under Heterogeneous User Preferences: An Effective Throughput Perspective.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

Source Coding at the Edge: User Preference Oriented Lossless Data Compression.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

2018
Multicast Pushing With Content Request Delay Information.
IEEE Trans. Commun., 2018

Coded Joint Pushing and Caching With Asynchronous User Requests.
IEEE J. Sel. Areas Commun., 2018

A Unified Framework for Caching in Arbitrary Networks.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2017
Joint Pushing and Caching Based on Physical Layer Multicasting and Network Coding.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

2016
Content Pushing Based on Physical Layer Multicasting and Request Delay Information.
Proceedings of the 2016 IEEE Global Communications Conference, 2016

2013
An integrated development environment for reconfigurable operators array.
Proceedings of the IEEE 10th International Conference on ASIC, 2013


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