Yen-Tai Lai

According to our database, Yen-Tai Lai authored at least 31 papers between 1984 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A High-Throughput JPEG XR Encoder.

Chao-Feng Tseng, Yen-Tai Lai

J. Signal Process. Syst., 2016

Fast coding unit decision and mode selection for intra-frame coding in high-efficiency video coding.

Chao-Feng Tseng, Yen-Tai Lai

IET Image Process., 2016

2014

Design of a 1-GSample/s 9-b double sampling track-and-hold amplifier in BiCMOS technology.

Hung-Yi Lin, Yen-Tai Lai

Int. J. Circuit Theory Appl., 2014

2013

Power minimization for dynamically reconfigurable FPGA partitioning.

Tzu-Chiang Tai, Yen-Tai Lai

ACM Trans. Embed. Comput. Syst., 2013

Design of Low Power Two-phase CMOS Buffer for Large capacitive loading Applications.

Hung-Yi Lin, Yen-Tai Lai

J. Circuits Syst. Comput., 2013

Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost Designs.

Chi-Chou Kao, Yen-Tai Lai

J. Circuits Syst. Comput., 2013

2012

Laplacian-based H.264 intra-prediction mode decision.

Chi-Chou Kao, Yen-Tai Lai, Chao-Feng Tseng

Proceedings of the 7th International Conference on Communications and Networking in China, 2012

2011

A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning.

Tzu-Chiang Tai, Yen-Tai Lai

ACM Trans. Reconfigurable Technol. Syst., 2011

A low distortion CMOS continuous-time common-mode feedback circuit.

Yen-Tai Lai, Hung-Yi Lin

Int. J. Circuit Theory Appl., 2011

2010

A Performance-Driven Rotational Invariant Image Retrieval System.

Yen-Tai Lai, Chi-Chou Kao, Tzu-Chiang Tai, Wen-Chun Yeh

J. Inf. Sci. Eng., 2010

An efficient reflection invariance region-based image retrieval framework.

Chi-Chou Kao, Yen-Tai Lai, Chia-Hui Lin

Int. J. Imaging Syst. Technol., 2010

2009

A Novel Digital Pixel Sensor System.

Yen-Tai Lai, Chia-Nan Yeh, Chi-Chou Kao

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

A novel flash analog-to-digital converter.

Chia-Nan Yeh, Yen-Tai Lai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006

Low power readout control circuit for high resolution CMOS image sensor.

Chia-Nan Yeh, Yen-Tai Lai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

An efficient algorithm for finding the minimal-area FPGA technology mapping.

Chi-Chou Kao, Yen-Tai Lai

ACM Trans. Design Autom. Electr. Syst., 2005

Placement for the reconfigurable datapath architecture.

Yen-Tai Lai, Hsin-Ya Lai, Chia-Nan Yeh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

BDD decomposition for mixed CMOS/PTL logic circuit synthesis.

Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction.

Chi-Chou Kao, Yen-Tai Lai

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A technology mapping algorithm for heterogeneous FPGAs.

Chi-Chou Kao, Yen-Tai Lai

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Design of the ordinary differential equation solver in the Yau filtering system.

Yen-Tai Lai, Stephen S.-T. Yau, Ping-Hua Chen

Proceedings of the American Control Conference, 2002

2001

Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints.

Lih-Yang Wang, Yen-Tai Lai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

1999

A quadratic programming method for interconnection crosstalk minimization.

Yen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A routability and performance driven technology mapping algorithm for LUT based FPGA designs.

Chi-Chou Kao, Yen-Tai Lai

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997

Hierarchical interconnection structures for field programmable gate arrays.

Yen-Tai Lai, Ping-Tsung Wang

IEEE Trans. Very Large Scale Integr. Syst., 1997

1995

Performance-directed compaction for VLSI symbolic layouts.

Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang

Comput. Aided Des., 1995

1994

A High Performance FPGA with Hierarchical Interconnection Structure.

Ping-Tsung Wang, Kun-Nen Chen, Yen-Tai Lai

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Layout Compaction with Minimzed Delay Bound on Timing Critical Paths.

Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths.

Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1990

A Theory of Rectangular Dual Graphs.

Yen-Tai Lai, Sany M. Leinwand

Algorithmica, 1990

1988

Algorithms for floorplan design via rectangular dualization.

Yen-Tai Lai, Sany M. Leinwand

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1984

An algorithm for building rectangular floor-plans.

Sany M. Leinwand, Yen-Tai Lai

Proceedings of the 21st Design Automation Conference, 1984