Bin-Da Liu

According to our database1, Bin-Da Liu authored at least 110 papers between 1992 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2006, "For contributions to very large scaled integrated (VLSI) processors for neural networks and video signal processing.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Stereoview to Multiview Conversion Architecture for Auto-Stereoscopic 3D Displays.
IEEE Trans. Circuits Syst. Video Technol., 2018

2017
Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Novel 10-Bit Impedance-to-Digital Converter for Electrochemical Impedance Spectroscopy Measurements.
IEEE Trans. Biomed. Circuits Syst., 2017

2016
Special issue on <i>Efficient video coding and beyond</i>.
Multidimens. Syst. Signal Process., 2016

High efficiency depth image-based rendering with simplified inpainting-based hole filling.
Multidimens. Syst. Signal Process., 2016

A Multi-Channel Electrochemical Measurement System for Biomolecular Detection.
IEICE Trans. Electron., 2016

New Power Factor Correction Application for a Small Wind Power System.
IEICE Trans. Electron., 2016

Comparative frequency response analysis system for electrochemical impedance spectroscopy measurements.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

An advanced 3D format generation architecture for video and depth.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
An Advanced Video and Depth Depacking Architecture for 3D Applications.
J. Inf. Sci. Eng., 2015

Fast three-dimensional video coding encoding algorithms based on edge information of depth map.
IET Image Process., 2015

An iterative enhanced super-resolution system with edge-dominated interpolation and adaptive enhancements.
EURASIP J. Adv. Signal Process., 2015

2014
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Wide-Range Filter-Based Sinusoidal Wave Synthesizer for Electrochemical Impedance Spectroscopy Measurements.
IEEE Trans. Biomed. Circuits Syst., 2014

Efficient residual coding algorithm based on hadamard transform in lossless H.264/AVC.
IET Image Process., 2014

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder.
IEICE Trans. Electron., 2014

A low supply voltage mixed-signal maximum power point tracking controller for photovoltaic power system.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013
A Simple Implementation of Nonlinear-Carrier Control for Power Factor Correction Rectifier With Variable Slope Ramp on Field-Programmable Gate Array.
IEEE Trans. Ind. Informatics, 2013

Novel automatic offset cancellation approach for capacitive CMOS MEMS accelerometers.
Proceedings of the IEEE International Symposium on Consumer Electronics, 2013

A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Design of a dual-mode electrochemical measurement and analysis system.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Inpainting-based multi-view synthesis algorithms and its GPU accelerated implementation.
Proceedings of the 9th International Conference on Information, 2013

2012
A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing.
IEICE Trans. Electron., 2012

Performance-driven analog placement considering monotonic current paths.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
Adaptive Truncation Algorithm for Hadamard-Transformed H.264/AVC Lossless Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2011

A Two-Stage Rate Control Mechanism for RDO-Based H.264/AVC Encoders.
IEEE Trans. Circuits Syst. Video Technol., 2011

Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A High Current Accuracy Boost White LED Driver Based on Offset Calibration Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A microfluidic and potentiostatic sensor integrated with neopterin-imprinted poly(ethylene-c0-vinyl alcohol) based electrode.
Proceedings of the 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2011

A microfluidic and potentiostatic sensor integrated with neopterin-imprinted poly(ethylene-co-vinyl alcohol) based electrode.
Proceedings of the 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2011

Design of a signal processing circuit for quartz crystal microbalance biosensors.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
An Efficient VLSI Architecture for Transform-Based Intra Prediction in H.264/AVC.
IEEE Trans. Circuits Syst. Video Technol., 2010

Hardware/Software Codesign of a Low-Cost Rate Control Scheme for H.264/AVC.
IEEE Trans. Circuits Syst. Video Technol., 2010

Classified Region Algorithm for Fast Intermode Decision in H.264/AVC Encoder.
EURASIP J. Adv. Signal Process., 2010

Low complexity MAD prediction algorithms for rate controllable H.264/AVC hardware encoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A high efficiency boost white LED driver with an integrated Schottky diode.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Combined CAVLC Decoder, Inverse Quantizer, and Transform Kernel in Compact H.264/AVC Decoder.
IEEE Trans. Circuits Syst. Video Technol., 2009

A High-Speed and EDP-Efficient Range-Matching Scheme for Packet Classification.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Breast Tumor Classification of Ultrasound Images Using a Reversible Round-Off Nonrecursive 1-D Discrete Periodic Wavelet Transform.
IEEE Trans. Biomed. Eng., 2009

Breast Tumor Classification of Ultrasound Images Using Wavelet-Based Channel Energy and ImageJ.
IEEE J. Sel. Top. Signal Process., 2009

Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Transform-domain Partial Prediction Algorithm for Intra Prediction in H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Design of One-cycle Control Power Factor Correction IC with Unipolar Supply Voltage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Lossless image and video coding based on H.264/AVC intra predictions with simplified interpolations.
Proceedings of the International Conference on Image Processing, 2009

2008
A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder.
IEEE Trans. Multim., 2008

A Low Complexity Detection of Discrete Cross Differences for Fast H.264/AVC Intra Prediction.
IEEE Trans. Multim., 2008

A Histogram-Based Testing Method for Estimating A/D Converter Performance.
IEEE Trans. Instrum. Meas., 2008

A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter.
IEICE Trans. Electron., 2008

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture.
IEICE Trans. Electron., 2008

Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

System level design of a spatio-temporal video resampling architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An approximate square criterion for H.264/AVC intra mode decision.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Transformed-based mode decision algorithm for H.264/AVC intraprediction.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Design of a green mode PWM control IC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST.
J. Electron. Test., 2007

Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Real Time and Low Cost Hardware Architecture for Video Abstraction System.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Novel Design for Computation of All Transforms in H.264/AVC Decoders.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

2006
A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Efficient deblocking filter architecture for H.264 video coders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low power design of H.264 CAVLC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A gray system modeling approach to the prediction of calibration intervals.
IEEE Trans. Instrum. Meas., 2005

DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation.
IEEE Trans. Circuits Syst. Video Technol., 2005

Condensed recursive structures for computing multidimensional DCT/IDCT with arbitrary length.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Combined 2-D transform and quantization architectures for H.264 video coders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Efficient recursive structures for forward and inverse discrete cosine transform.
IEEE Trans. Signal Process., 2004

Direct recursive structures for computing radix-r two-dimensional DCT/IDCT/DST/IDST.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Coefficients Generation for the 4th-Order Leapfrog Sigma-Delta A/D Converters.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2004

A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Unified selectable fixed-coefficient recursive structures for computing DCT, IMDCT and subband synthesis filtering.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Condensed recursive structures for computing multi-dimensional DCT with arbitrary length.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
A fuzzy-based impulse noise detection and cancellation for real-time processing in video receivers.
IEEE Trans. Instrum. Meas., 2003

Circuit implementation of linguistic-hedge fuzzy logic controller in current-mode approach.
IEEE Trans. Fuzzy Syst., 2003

Adaptive postprocessors with DCT-based block classifications.
IEEE Trans. Circuits Syst. Video Technol., 2003

Recursive architectures for realizing modified discrete cosine transform and its inverse.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

Low-power and low-voltage fully parallel content-addressable memory.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Direct recursive structures for computing radix-r two-dimensional DCT.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A scalable sorting architecture based on maskable WTA/MAX circuit.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design of a pipelined and expandable sorting architecture with simple control scheme.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

The high-resolution multi-tone signal generators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
Design of adaptive fuzzy logic controller based on linguistic-hedge concepts and genetic algorithms.
IEEE Trans. Syst. Man Cybern. Part B, 2001

A new level converter for low-power applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A hardware design approach for merge-sorting network.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1998
A graph representation for programmable logic arrays to facilitate testing and logic design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997
Design and implementation of the tree-based fuzzy logic controller.
IEEE Trans. Syst. Man Cybern. Part B, 1997

Hardware implementation of CMAC neural network with reduced storage requirement.
IEEE Trans. Neural Networks, 1997

Efficient postprocessor for blocky effect removal based on transform characteristics.
IEEE Trans. Circuits Syst. Video Technol., 1997

A fuzzy CMAC model for color reproduction.
Fuzzy Sets Syst., 1997

1996
A parallel video converter for displaying 4: 3 images on 16: 9 HDTV receivers.
IEEE Trans. Circuits Syst. Video Technol., 1996

Design of a color reproduction neural network chip with on-chip learning capability.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

1995
A practical current sensing technique for I<sub>DDQ</sub> testing.
IEEE Trans. Very Large Scale Integr. Syst., 1995

VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor.
IEEE Trans. Circuits Syst. Video Technol., 1995

Performance-directed compaction for VLSI symbolic layouts.
Comput. Aided Des., 1995

An I<sub>DDQ</sub> Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs).
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Hardware realization of higher-order CMAC model for color calibration.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

Built-in intermediate voltage testing for CMOS circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Combining the Folding and Testing for Programmable Logic Arrays.
J. Circuits Syst. Comput., 1994

Array Based Fuzzy Inference Mechanism Implemented with Current-Mode CMOS Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Layout Compaction with Minimzed Delay Bound on Timing Critical Paths.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Functional Text Pattern Generation for Asynchronous Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Overall consideration of scan design and test generation.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992


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