Yeo Myung Kim

According to our database, Yeo Myung Kim authored at least 4 papers between 2013 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2017

A 0.008-mm², 35-μW, 8.87-ps-resolution CMOS time-to-digital converter using dual-slope architecture.

Yeo Myung Kim, Doohyun Shon, Tae Wook Kim

Int. J. Circuit Theory Appl., 2017

2015

A 0.02mm² embedded temperature sensor with ±2°C inaccuracy for self-refresh control in 25nm mobile DRAM.

Yeo Myung Kim, Woojun Choi, Jaehoon Kim, Sanghoon Lee, Sangho Lee, Hyeongon Kim, Kofi A. A. Makinwa, Youngcheol Chae, Tae Wook Kim

Proceedings of the ESSCIRC Conference 2015, 2015

2014

An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space.

Yeo Myung Kim, Tae Wook Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

A 0.6-V +4 dBm IIP3 LC Folded Cascode CMOS LNA With g_m Linearization.

Yeo Myung Kim, Hong Gul Han, Tae Wook Kim

IEEE Trans. Circuits Syst. II Express Briefs, 2013