Yi-Su Chung

According to our database, Yi-Su Chung authored at least 1 paper in 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging.

Poki Chen, Ya-Yun Hsiao, Yi-Su Chung, Wei Xiang Tsai, Jhih-Min Lin

IEEE Trans. Very Large Scale Integr. Syst., 2017