Poki Chen

According to our database1, Poki Chen authored at least 20 papers between 1991 and 2019.

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Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display.
J. Solid-State Circuits, 2019

On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs.
Proceedings of the IEEE International Test Conference in Asia, 2019

2018
Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

2017
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

2015
A multi-channel high precision current matching LED Driver for intelligent dimming.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

A 486k S/s CMOS time-domain smart temperature sensor with -0.85°C/0.78°C voltage-calibrated error.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2011
All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of -0.7~°C - +0.6~°C After One-Point Calibration.
IEEE Trans. on Circuits and Systems, 2011

2010
FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range.
IEEE Trans. on Circuits and Systems, 2010

A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of -0.4°C ∼ +0.6°C Over a 0°C to 90°C Range.
J. Solid-State Circuits, 2010

2009
Switching Schemes for Reducing Capacitor Mismatch Sensitivity of Quasi-Passive Cyclic DAC.
IEEE Trans. on Circuits and Systems, 2009

2008
A FPGA vernier digital-to-time converter with 3.56ps resolution and -0.23∼+0.2LSB inaccuracy.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Fully Digital Time-Domain Smart Temperature Sensor Realized With 140 FPGA Logic Elements.
IEEE Trans. on Circuits and Systems, 2007

2006
A Time Domain Mixed-Mode Temperature Sensor with Digital Set-Point Programming.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A time-to-digital-converter-based CMOS smart temperature sensor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A wide-range and fast-locking clock synthesizer IP based on delay-locked loop.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A high-resolution and fast-conversion time-to-digital converter.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

1991
An improved transmission protocol for two interfering queues in packet radio networks.
IEEE Trans. Communications, 1991


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