Yifeng Kuai

According to our database, Yifeng Kuai authored at least 2 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur.

Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada

IEEE J. Solid State Circuits, June, 2025

2024

10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.

Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada

Proceedings of the IEEE International Solid-State Circuits Conference, 2024