Yuncheng Zhang

According to our database1, Yuncheng Zhang authored at least 11 papers between 2014 and 2021.

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Bibliography

2021
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems.
IEEE J. Solid State Circuits, 2021

32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A DSM-based Polar Transmitter with 23.8% System Efficiency.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Synergetic governing controller design for the hydraulic turbine governing system with complex conduit system.
J. Frankl. Inst., 2018

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A parameter adaptive identification method for a pumped storage hydro unit regulation system model using an improved gravitational search algorithm.
Simul., 2017

2015
A Multibit Delta-Sigma Modulator With Double Noise-Shaped Segmentation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014
Digital Noise-Coupling Technique for Delta-Sigma Modulators With Segmented Quantization.
IEEE Trans. Circuits Syst. II Express Briefs, 2014


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