Ashbir Aviat Fadila
Orcid: 0000-0002-5529-8217Affiliations:
- Tokyo Institute of Technology, Japan
According to our database1,
Ashbir Aviat Fadila
authored at least 23 papers
between 2019 and 2024.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2024
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter.
IEEE J. Solid State Circuits, April, 2024
A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation.
IEEE J. Solid State Circuits, February, 2024
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations.
IEEE J. Solid State Circuits, December, 2023
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR.
IEEE J. Solid State Circuits, 2022
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal.
IEEE J. Solid State Circuits, 2022
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation.
IEEE J. Solid State Circuits, 2022
A 28-GHz Fully-Passive Retro-Reflective Phased-Array Backscattering Transceiver for 5G Network with 24-GHz Beam-Steered Wireless Power Transfer.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems.
IEEE J. Solid State Circuits, 2021
22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR.
IEEE J. Solid State Circuits, 2020
A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019