Yindan Jiang
According to our database1,
Yindan Jiang authored at least 2 papers
in 2026.
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Bibliography
2026
A 14-bit 1.25GS/s single-channel pipelined ADC with distributed differential reference voltage buffer and hybrid mixed-signal foreground and background calibration.
Microelectron. J., 2026
A 16-bit 210 MS/s pipelined ADC with distributed differential reference voltage buffer and foreground calibration.
IEICE Electron. Express, 2026