Yintao Liu
Orcid: 0009-0002-3538-4676Affiliations:
- Shanghai University, School of Communication and Information Engineering, China
According to our database1,
Yintao Liu authored at least 10 papers
between 2024 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2026
Venusian: Rapid Wireless Baseband Validation via High-Level Programming and FPGA-Based RISC-V Accelerator Co-Design.
IEEE Trans. Very Large Scale Integr. Syst., June, 2026
An Agile Systolic Array-Based Hardware Accelerator for Scalable Multi-Head Self-Attention.
IEEE Embed. Syst. Lett., April, 2026
Late Breaking Results: A Power-Efficient RISC-V Baseband System-on-Chip for Multi-Standard Integrated Sensing and Communications.
Proceedings of the Design, Automation & Test in Europe Conference, 2026
2025
Venus: A RISC-V Domain Specific Architecture Towards Integrated AI and Wireless Baseband Processing for 6G Edge Intelligence.
IEEE Wirel. Commun., December, 2025
A Heterogeneous CNN Compilation Framework for RISC-V CPU and NPU Integration Based on ONNX-MLIR.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2025
(Artifact) Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP).
Dataset, April, 2025
(Artifact) Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP).
Dataset, April, 2025
Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP).
Proceedings of the 26th ACM SIGPLAN/SIGBED International Conference on Languages, 2025
A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing.
CoRR, 2024