Yiran Chen

According to our database1, Yiran Chen authored at least 300 papers between 2002 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2018, "For contributions to spintronic memory".

Timeline

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Links

On csauthors.net:

Bibliography

2019
Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses.
IEEE Trans. Computers, 2019

A color image cryptosystem based on dynamic DNA encryption and chaos.
Signal Processing, 2019

A novel image encryption scheme based on DNA sequence operations and chaotic systems.
Neural Computing and Applications, 2019

Reshaping Future Computing Systems With Emerging Nonvolatile Memory Technologies.
IEEE Micro, 2019

D3-LND: A two-stream framework with discriminant deep descriptor, linear CMDT and nonlinear KCMDT descriptors for action recognition.
Neurocomputing, 2019

Low-Power Computer Vision: Status, Challenges, and Opportunities.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Building a model-based personalised recommendation approach for tourist attractions from geotagged social media data.
Int. J. Digital Earth, 2019

Test-Retest Reliability of Graph Theoretic Metrics in Adolescent Brains.
Brain Connectivity, 2019

Markov Chain Based Efficient Defense Against Adversarial Examples in Computer Vision.
IEEE Access, 2019

HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

RED: A ReRAM-based Deconvolution Accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Adaptive Granularity Encoding for Energy-efficient Non-Volatile Main Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

MobiEye: An Efficient Cloud-based Video Detection System for Real-time Mobile Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Towards Decentralized Deep Learning with Differential Privacy.
Proceedings of the Cloud Computing - CLOUD 2019, 2019

NeuralHMC: an efficient HMC-based accelerator for deep neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

AdverQuil: an efficient adversarial detection and alleviation technique for black-box neuromorphic computing systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Bamboo: Ball-Shape Data Augmentation Against Adversarial Attacks from All Directions.
Proceedings of the Workshop on Artificial Intelligence Safety 2019 co-located with the Thirty-Third AAAI Conference on Artificial Intelligence 2019 (AAAI-19), 2019

DPATCH: An Adversarial Patch Attack on Object Detectors.
Proceedings of the Workshop on Artificial Intelligence Safety 2019 co-located with the Thirty-Third AAAI Conference on Artificial Intelligence 2019 (AAAI-19), 2019

2018
HiSpatialCluster: A novel high-performance software tool for clustering massive spatial points.
Trans. GIS, 2018

Improving Write Performance and Extending Endurance of Object-Based NAND Flash Devices.
ACM Trans. Embedded Comput. Syst., 2018

TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

An image encryption algorithm based on chaotic system and compressive sensing.
Signal Processing, 2018

A new framework of action recognition with discriminative parts, spatio-temporal and causal interaction descriptors.
J. Visual Communication and Image Representation, 2018

Shift-Optimized Energy-Efficient Racetrack-Based Main Memory.
Journal of Circuits, Systems, and Computers, 2018

Neuromorphic computing's yesterday, today, and tomorrow - an evolutional view.
Integration, 2018

NV-TCAM: Alternative designs with NVM devices.
Integration, 2018

A Forgetting Memristive Spiking Neural Network for Pavlov Experiment.
I. J. Bifurcation and Chaos, 2018

Survey of Low-Power Electric Vehicles: A Design Automation Perspective.
IEEE Design & Test, 2018

Challenges of memristor based neuromorphic computing system.
SCIENCE CHINA Information Sciences, 2018

Low-Power Image Recognition Challenge.
AI Magazine, 2018

Building a Spatially-Embedded Network of Tourism Hotspots From Geotagged Social Media Data.
IEEE Access, 2018

A Spark-Based High Performance Computational Approach for Simulating Typhoon Wind Fields.
IEEE Access, 2018

Special session on reliability and vulnerability of neuromorphic computing systems.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Generalized Inverse Optimization through Online Learning.
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design and Data Management for Magnetic Racetrack Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Learning Intrinsic Sparse Structures within Long Short-Term Memory.
Proceedings of the 6th International Conference on Learning Representations, 2018

RouteNet: routability prediction for mixed-size designs using convolutional neural network.
Proceedings of the International Conference on Computer-Aided Design, 2018

SPN dash: fast detection of adversarial attacks on mobile via sensor pattern noise fingerprinting.
Proceedings of the International Conference on Computer-Aided Design, 2018

RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

GraphR: Accelerating Graph Processing Using ReRAM.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Real-Time Cardiac Arrhythmia Classification Using Memristor Neuromorphic Computing System.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ReRAM-based accelerator for deep learning.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ReCom: An efficient resistive accelerator for compressed deep neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Three years of low-power image recognition challenge: Introduction to special session.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research.
Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-designing Pareto-efficient Deep Learning, 2018

Keynote.
Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-designing Pareto-efficient Deep Learning, 2018

Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Running sparse and low-precision neural network: When algorithm meets hardware.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Spintronics based stochastic computing for efficient Bayesian inference system.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Process variation aware data management for magnetic skyrmions racetrack memory.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Data-Pattern-Aware Error Prevention Technique to Improve System Reliability.
IEEE Trans. VLSI Syst., 2017

Exploiting Multiple Write Modes of Nonvolatile Main Memory in Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2017

Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.
IEEE Trans. Computers, 2017

Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache.
IEEE Trans. Computers, 2017

An image encryption algorithm based on the memristive hyperchaotic system, cellular automata and DNA sequence operations.
Sig. Proc.: Image Comm., 2017

A visually secure image encryption scheme based on compressive sensing.
Signal Processing, 2017

Heuristic hybrid game approach for fleet condition-based maintenance planning.
Rel. Eng. & Sys. Safety, 2017

Giant Spin-Hall assisted STT-RAM and logic design.
Integration, 2017

Forgetting memristor based neuromorphic system for pattern training and recognition.
Neurocomputing, 2017

GeoSpark SQL: An Effective Framework Enabling Spatial Queries on Spark.
ISPRS Int. J. Geo-Information, 2017

Recent Technology Advances of Emerging Memories.
IEEE Design & Test, 2017

Guest Editors' Introduction: Critical and Enabling Techniques for Emerging Memories.
IEEE Design & Test, 2017

Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.
IEEE Consumer Electronics Magazine, 2017

Cooperative game approach based on agent learning for fleet maintenance oriented to mission reliability.
Computers & Industrial Engineering, 2017

MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A quantization-aware regularized learning method in multilevel memristor-based neuromorphic computing system.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning.
Proceedings of the Advances in Neural Information Processing Systems 30: Annual Conference on Neural Information Processing Systems 2017, 2017

A lightweight progress maximization scheduler for non-volatile processor under unstable energy harvesting.
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017

Hardware implementation of echo state networks using memristor double crossbar arrays.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Behaviors of multi-dimensional forgetting memristor models.
Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017

Faster CNNs with Direct Sparse Convolutions and Guided Pruning.
Proceedings of the 5th International Conference on Learning Representations, 2017

Coordinating Filters for Faster Deep Neural Networks.
Proceedings of the IEEE International Conference on Computer Vision, 2017

A closed-loop design to enhance weight stability of memristor based neural network chips.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

VoCaM: Visualization oriented convolutional neural network acceleration on mobile system: Invited paper.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

AdaLearner: An adaptive distributed mobile learning system for neural networks.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

An ensemble approach to activity recognition based on binary sensor readings.
Proceedings of the 19th IEEE International Conference on e-Health Networking, 2017

An FPGA Design Framework for CNN Sparsification and Acceleration.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

MoDNN: Local distributed mobile computing system for Deep Neural Network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Compact DNN: Approaching GoogLeNet-Level Accuracy of Classification and Domain Adaptation.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition, 2017

Low-power neuromorphic speech recognition engine with coarse-grain sparsity.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.
IEEE Trans. on Circuits and Systems, 2016

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Statistical Cache Bypassing for Non-Volatile Memory.
IEEE Trans. Computers, 2016

The bipolar and unipolar reversible behavior on the forgetting memristor model.
Neurocomputing, 2016

ApesNet: a pixel-wise efficient segmentation network for embedded devices.
IET Cyper-Phys. Syst.: Theory & Appl., 2016

Spintronic Memristor as Interface Between DNA and Solid State Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Practical power consumption analysis with current smartphones.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Spin-Hall Assisted STT-RAM Design and Discussion.
Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

Objnandsim: object-based NAND flash device simulator.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Learning Structured Sparsity in Deep Neural Networks.
Proceedings of the Advances in Neural Information Processing Systems 29: Annual Conference on Neural Information Processing Systems 2016, 2016

Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A neuromorphic ASIC design using one-selector-one-memristor crossbar.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Security of neuromorphic systems: Challenges and solutions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Heterogeneous systems with reconfigurable neuromorphic computing accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Built-in selectors self-assembled into memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Adaptive refreshing and read voltage control scheme for FeDRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Neural processor design enabled by memristor technology.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Design techniques of eNVM-enabled neuromorphic computing systems.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Security challenges in smart surveillance systems and the solutions based on emerging nano-devices.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Scope - quality retaining display rendering workload scaling based on user-smartphone distance.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

SC-ESAP: A Parallel Application Platform for Earth System Model.
Proceedings of the International Conference on Computational Science 2016, 2016

Modeling STT-RAM fabrication cost and impacts in NVSim.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

The Applications of NVM Technology in Hardware Security.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

ApesNet: A Pixel-wise Efficient Segmentation Network.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

Dictionary learning for sparse representation and classification of neural spikes.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip.
Proceedings of the 53rd Annual Design Automation Conference, 2016

TEMP: thread batch enabled memory partitioning for GPU.
Proceedings of the 53rd Annual Design Automation Conference, 2016

NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

MORPh: mobile OLED-friendly recording and playback system for low power video streaming.
Proceedings of the 53rd Annual Design Automation Conference, 2016

AOS: adaptive overwrite scheme for energy-efficient MLC STT-RAM cache.
Proceedings of the 53rd Annual Design Automation Conference, 2016

A design to reduce write amplification in object-based NAND flash devices.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

A novel PUF based on cell error rate distribution of STT-RAM.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Thermal optimization for memristor-based hybrid neuromorphic computing systems.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

SlowMo - enhancing mobile gesture-based authentication schemes via sampling rate optimization.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Footfall - GPS polling scheduler for power saving on wearable devices.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Read Performance: The Newest Barrier in Scaled STT-RAM.
IEEE Trans. VLSI Syst., 2015

Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing.
IEEE Trans. Multi-Scale Computing Systems, 2015

RRAM-Based Analog Approximate Computing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache.
IEEE Trans. Computers, 2015

Reconfigurable Neuromorphic Computing System with Memristor-Based Synapse Design.
Neural Processing Letters, 2015

Circuit design and exponential stabilization of memristive neural networks.
Neural Networks, 2015

Effects of rejecting diffusion directions on tensor-derived parameters.
NeuroImage, 2015

Multi-agent-based smart cargo tracking system.
IJHPCN, 2015

Hardware acceleration for neuromorphic computing: An evolving view.
Proceedings of the 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 2015

Fork path: improving efficiency of ORAM by removing redundant memory accesses.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Memristor Crossbar Array for Image Storing.
Proceedings of the Advances in Neural Networks - ISNN 2015, 2015

A new self-reference sensing scheme for TLC MRAM.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

The applications of memristor devices in next-generation cortical processor designs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

EDA Challenges for Memristor-Crossbar based Neuromorphic Computing.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Accelerating generation of stochastic cyclone routes with GPU programming.
Proceedings of the 23rd International Conference on Geoinformatics, 2015

Giant spin hall effect (GSHE) logic design for low power application.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Spiking neural network with RRAM: can we use it for real-world application?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An EDA framework for large scale hybrid neuromorphic computing systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A spiking neuromorphic design with resistive crossbar.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Cloning your mind: security challenges in cognitive system designs and their solutions.
Proceedings of the 52nd Annual Design Automation Conference, 2015

RENO: a high-efficient reconfigurable neuromorphic computing accelerator design.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Vortex: variation-aware training for memristor X-bar.
Proceedings of the 52nd Annual Design Automation Conference, 2015

FlexLevel: a novel NAND flash storage system design for LDPC latency reduction.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Area and performance co-optimization for domain wall memory in application-specific embedded systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Spiking-based matrix computation by leveraging memristor crossbar array.
Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015

Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

An efficient STT-RAM-based register file in GPU architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Recent progresses of STT memory design and applications.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
User Classification and Authentication for Mobile Device Based on Gesture Recognition.
Proceedings of the Network Science and Cybersecurity, 2014

Memristor Crossbar-Based Neuromorphic Computing System: A Case Study.
IEEE Trans. Neural Netw. Learning Syst., 2014

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Memristor crossbar-based unsupervised image learning.
Neural Computing and Applications, 2014

NV-TCAM: Alternative interests and practices in NVM designs.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Memristive Radial Basis Function Neural Network for Parameters Adjustment of PID Controller.
Proceedings of the Advances in Neural Networks - ISNN 2014, 2014

SBAC: a statistics based cache bypassing method for asymmetric-access caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper).
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Bio-inspired computing with resistive memories - models, architectures and applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An adjustable memristor model and its application in small-world neural networks.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

STDP learning rule based on memristor with STDP property.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Reduction of data prevention cost and improvement of reliability in MLC NAND flash storage system.
Proceedings of the International Conference on Computing, Networking and Communications, 2014

Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A heterogeneous computing system with memristor-based neuromorphic accelerators.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Mobile GPU Power Consumption Reduction via Dynamic Resolution and Frame Rate Scaling.
Proceedings of the 6th Workshop on Power-Aware Computing and Systems, 2014

FingerShadow: An OLED Power Optimization Based on Smartphone Touch Interactions.
Proceedings of the 6th Workshop on Power-Aware Computing and Systems, 2014

ICE: Inline calibration for memristor crossbar-based computing engine.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy efficient neural networks for big data analytics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

eButton: A Wearable Computer for Health Monitoring and Personal Assistance.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Demystifying Energy Usage in Smartphones.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

3M-PCM: Exploiting multiple write modes MLC phase change main memory in embedded systems.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Prefetching techniques for STT-RAM based last-level cache in CMP systems.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Training itself: Mixed-signal training acceleration for memristor-based neural network.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

DPA: A data pattern aware error prevention technique for NAND flash lifetime extension.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.
ACM Trans. Design Autom. Electr. Syst., 2013

Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.
ACM Trans. Design Autom. Electr. Syst., 2013

C1C: A configurable, compiler-guided STT-RAM L1 cache.
TACO, 2013

Online OLED dynamic voltage scaling for video streaming applications on mobile devices.
SIGBED Review, 2013

Reliability-aware energy minimization for real-time embedded systems with window-constraints.
SIGBED Review, 2013

Global exponential synchronization of memristor-based recurrent neural networks with time-varying delays.
Neural Networks, 2013

Passivity analysis of memristor-based recurrent neural networks with time-varying delays.
J. Franklin Institute, 2013

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.
JETC, 2013

Fast Position and Accurate Segmentation Algorithms for Detecting Surface Defects of the Thermal-State Heavy Rail Based on Machine Vision.
IJSSCI, 2013

How is energy consumed in smartphone display applications?
Proceedings of the 14th Workshop on Mobile Computing Systems and Applications, 2013

Memristor-based approximated computation.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

MLC STT-RAM design considering probabilistic and asymmetric MTJ switching.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Considering fabrication in sustainable computing.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Cache coherence enabled adaptive refresh for volatile STT-RAM.
Proceedings of the Design, Automation and Test in Europe, 2013

Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer.
Proceedings of the Design, Automation and Test in Europe, 2013

DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Online OLED dynamic voltage scaling for video streaming applications on mobile devices.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

BSB training scheme implementation on memristor-based circuit.
Proceedings of the 2013 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2013

Loadsa: A yield-driven top-down design method for STT-RAM array.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Mobile user classification and authorization based on gesture usage recognition.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Compiler-assisted refresh minimization for volatile STT-RAM cache.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Low-Power Design of Emerging Memory Technologies.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory.
IEEE Trans. VLSI Syst., 2012

Quantitative Study of Individual Emotional States in Social Networks.
IEEE Trans. Affective Computing, 2012

A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme.
J. Solid-State Circuits, 2012

Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder.
JETC, 2012

Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration.
Embedded Systems Letters, 2012

Neuromorphic computing: A SoC scaling path for the next decades.
Proceedings of the IEEE 25th International SOC Conference, 2012

Utilizing PCM for Energy Optimization in Embedded Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Improving energy efficiency of write-asymmetric memories by log style write.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

A software approach for combating asymmetries of non-volatile memories.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Memristor crossbar based hardware realization of BSB recall function.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

The Circuit Realization of a Neuromorphic Computing System with Memristor-Based Synapse Design.
Proceedings of the Neural Information Processing - 19th International Conference, 2012

Multi-level cell STT-RAM: Is it realistic or just a dream?
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

A thermal and process variation aware MTJ switching model and its applications in soft error analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Mobile devices user - The subscriber and also the publisher of real-time OLED display power management plan.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Architecting a common-source-line array for bipolar non-volatile memory devices.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Asymmetry of MTJ switching and its implication to STT-RAM designs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Spintronic memristor based temperature sensor design with CMOS current reference.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Statistical memristor modeling and case study in neuromorphic computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Probabilistic design in spintronic memory and logic circuit.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Fine-grained dynamic voltage scaling on OLED display.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM).
IEEE Trans. VLSI Syst., 2011

Spintronic Memristor: Compact Model and Statistical Analysis.
J. Low Power Electronics, 2011

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.
IET Computers & Digital Techniques, 2011

Maximum Profit Configurations of Commercial Engines.
Entropy, 2011

Processor caches with multi-level spin-transfer torque ram cells.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers.
Proceedings of the Design, Automation and Test in Europe, 2011

Emerging non-volatile memories: opportunities and challenges.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Geometry variations analysis of TiO2 thin-film and spintronic memristors.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Emerging sensing techniques for emerging memories.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed.
IEEE Trans. VLSI Syst., 2010

Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies.
IEEE Trans. VLSI Syst., 2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.
IEEE Trans. VLSI Syst., 2010

Scalability of PCMO-based resistive switch device in DSM technologies.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Low-power dual-element memristor based memory design.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

MoodCast: Emotion Prediction via Dynamic Continuous Factor Graph Model.
Proceedings of the ICDM 2010, 2010

Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Spintronic memristor devices and application.
Proceedings of the Design, Automation and Test in Europe, 2010

A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM).
Proceedings of the Design, Automation and Test in Europe, 2010

Impact of process variations on emerging memristor.
Proceedings of the 47th Design Automation Conference, 2010

2009
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.
IEEE Trans. VLSI Syst., 2009

Tolerating process variations in large, set-associative caches: The buddy cache.
TACO, 2009

Compact modeling and corner analysis of spintronic memristor.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.
Proceedings of the 27th International Conference on Computer Design, 2009

A novel architecture of the 3D stacked MRAM L2 cache for CMPs.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

An overview of non-volatile memory technology and the implication for tools and architectures.
Proceedings of the Design, Automation and Test in Europe, 2009

Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.
Proceedings of the 46th Design Automation Conference, 2009

2008
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM).
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
Proceedings of the 45th Design Automation Conference, 2008

2007
Statistical Timing Analysis Considering Spatial Correlations.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

VOSCH: Voltage scaled cache hierarchies.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.
IEEE Trans. VLSI Syst., 2005

Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Statistical based link insertion for robust clock network design.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Trans. VLSI Syst., 2004

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Deterministic Clock Gating for Microprocessor Power Reduction.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods.
Proceedings of the 2002 Design, 2002


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