Yohei Nakata
According to our database1,
Yohei Nakata
authored at least 29 papers
between 2010 and 2024.
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Bibliography
2024
VeCAF: VLM-empowered Collaborative Active Finetuning with Training Objective Awareness.
CoRR, 2024
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
Efficient Deweahter Mixture-of-Experts with Uncertainty-Aware Feature-Wise Linear Modulation.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
Efficient Deweather Mixture-of-Experts with Uncertainty-aware Feature-wise Linear Modulation.
CoRR, 2023
CoRR, 2023
Concurrent Misclassification and Out-of-Distribution Detection for Semantic Segmentation via Energy-Based Normalizing Flow.
Proceedings of the Uncertainty in Artificial Intelligence, 2023
2022
Proceedings of the Computer Vision - ECCV 2022, 2022
2021
Lossless AI: Toward Guaranteeing Consistency between Inferences Before and After Quantization via Knowledge Distillation.
Proceedings of the 17th International Conference on Machine Vision and Applications, 2021
2020
RandomNet: Towards Fully Automatic Neural Architecture Design for Multimodal Learning.
CoRR, 2020
2015
IEICE Trans. Electron., 2015
2014
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron., 2014
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM.
Proceedings of the ARCS 2014, 2014
2013
Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM.
IEICE Trans. Electron., 2013
Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme.
IPSJ Trans. Syst. LSI Des. Methodol., 2012
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing.
IEICE Trans. Electron., 2012
IEICE Electron. Express, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
2011
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010