Yoshikazu Saito

According to our database, Yoshikazu Saito authored at least 4 papers between 1989 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs.

Chizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko

IEICE Trans. Electron., 2013

2000

Graeco-Latin squares design for line detection in the presence of correlated noise.

Gerard J. Genello, Julian F. Y. Cheung, Steven H. Billis, Yoshikazu Saito

IEEE Trans. Image Process., 2000

1991

A 17-ns 4-Mb CMOS DRAM.

Takeshi Nagai, Kenji Numata, Masaki Ogihara, Mitsuru Shimizu, Kimimasa Imai, Takahiko Hara, Munehiro Yoshida, Yoshikazu Saito, Yoshiaki Asao, Shizuo Sawada, Syuso Fujii

IEEE J. Solid State Circuits, November, 1991

1989

A 45-ns 16-Mbit DRAM with triple-well structure.

Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshikawa, Sejii Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto, Koichi Toita

IEEE J. Solid State Circuits, October, 1989