Yoshinori Takano

According to our database, Yoshinori Takano authored at least 5 papers between 2000 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2002

A 44-mm² four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller.

Toru Tanzawa, Akira Umezawa, Tadayuki Taura, Hitoshi Shiga, Tokumasa Hara, Yoshinori Takano, Takeshi Miyaba, Naoya Tokiwa, Kentaro Watanabe, Hiroshi Watanabe, Kazunori Masuda, Kiyomi Naruke, Hideo Kato, Shigeru Atsumi

IEEE J. Solid State Circuits, 2002

High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories.

Toru Tanzawa, Yoshinori Takano, Kentaro Watanabe, Shigeru Atsumi

IEEE J. Solid State Circuits, 2002

2001

Wordline voltage generating system for low-power low-voltage flash memories.

Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi

IEEE J. Solid State Circuits, 2001

2000

Design of a sense circuit for low-voltage flash memories.

Toru Tanzawa, Yoshinori Takano, Tadayuki Taura, Shigeru Atsumi

IEEE J. Solid State Circuits, 2000

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme.

Shigeru Atsumi, Akira Umezawa, Tooru Tanzawa, Tadayuki Taura, Hitoshi Shiga, Yoshinori Takano, Takeshi Miyaba, Michiharu Matsui, Hiroshi Watanabe, Kazuaki Isobe, Shota Kitamura, Seiji Yamada, Masanobu Saito, Seiichi Mori, Toshiharu Watanabe

IEEE J. Solid State Circuits, 2000