Young-Jun Park

According to our database, Young-Jun Park authored at least 9 papers between 2015 and 2018.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2018

All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator.

Young Jun Park, Parth Parekh, Fei Yuan

Microelectron. J., 2018

2017

Two-step pulse-shrinking time-to-digital converter.

Young Jun Park, Fei Yuan

Microelectron. J., 2017

All-digital ΔΣ TDC with differential bi-directional gated-delay-line time integrator.

Young Jun Park, Fei Yuan

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

1-1 MASH ΔΣ time-to-digital converter with differential cascode time integrator.

Young Jun Park, Fei Yuan

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integrator.

Young Jun Park, Fei Yuan

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016

Time integrator for mixed-mode signal processing.

Young Jun Park, Durand Jarrett-Amor, Fei Yuan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Time-mode techniques for fast-locking phase-locked loops.

Durand Jarrett-Amor, Young Jun Park, Fei Yuan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

A 12.88 MS/s 0.28 pJ/conv.step 8-bit stage-interleaved pulse-shrinking time-to-digital converter in 130 nm CMOS.

Young Jun Park, Fei Yuan

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

0.25-4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme.

Young Jun Park, Fei Yuan

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015