Yu-Ting Huang
Affiliations:- Powerchip Technology Corporation, Hsinchu, Taiwan
- National Chiao Tung University, Institute of Electronics, Hsinchu, Taiwan
According to our database1,
Yu-Ting Huang
authored at least 5 papers
between 2015 and 2018.
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Bibliography
2018
Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications.
IEICE Trans. Electron., 2018
2017
Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs.
IEICE Trans. Electron., 2017
2016
ESD protection design for the 45-V pLDMOS-SCR (p-n-p-arranged) devices with source-discrete distributions.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
2015
ESD reliability building in 0.25 μm 60-V p-channel LDMOS DUTs with different embedded SCRs.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015
Anti-ESD impacts on 60-V P-channel LDMOS devices as none-ODs zone inserting in the bulk region.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015