Yu Zhao

Orcid: 0000-0003-4377-5298

Affiliations:

HiSilicon, Shanghai, China
University of California Los Angeles (UCLA), Department of Electrical and Computer Engineering, CA, USA (PhD 2022)
Ubilinx Technology, Inc., San Jose, CA, USA (2015-2018)

According to our database¹, Yu Zhao authored at least 11 papers between 2019 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

A Low-Power 28-GHz Beamforming Receiver With On-Chip LO Synthesis.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, June, 2026

2023

A 56-GHz Fractional-N PLL With 110-fs Jitter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2023

A 20-GHz PLL With 20.9-fs Random Jitter.

[BibT_eX]

[DOI]

Yu Zhao

Mahdi Forghani

Behzad Razavi

IEEE J. Solid State Circuits, 2023

A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation.

[BibT_eX]

[DOI]

Onur Memioglu

Yu Zhao

Behzad Razavi

IEEE J. Solid State Circuits, 2023

A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Low-Power 28-GHz Beamforming Receiver with On-Chip LO Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A 56GHz 23mW Fractional-N PLL with 110fs Jitter.

[BibT_eX]

[DOI]

Yu Zhao

Onur Memioglu

Behzad Razavi

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 300GHz 52mW CMOS Receiver with On-Chip LO Generation.

[BibT_eX]

[DOI]

Onur Memioglu

Yu Zhao

Behzad Razavi

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Phase Noise Integration Limits for Jitter Calculation.

[BibT_eX]

[DOI]

Yu Zhao

Behzad Razavi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

A 19-GHz PLL with 20.3-fs Jitter.

[BibT_eX]

[DOI]

Yu Zhao

Behzad Razavi

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2019

A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Yu Zhao

Timeline

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Bibliography

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