Yuanlin Lu

According to our database, Yuanlin Lu authored at least 5 papers between 2004 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation.

Yuanlin Lu, Vishwani D. Agrawal

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Statistical Leakage and Timing Optimization for Submicron Process Variation.

Yuanlin Lu, Vishwani D. Agrawal

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff.

Yuanlin Lu, Vishwani D. Agrawal

J. Low Power Electron., 2006

2005

Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V_th Assignment and Path Balancing.

Yuanlin Lu, Vishwani D. Agrawal

Proceedings of the Integrated Circuit and System Design, 2005

2004

Decentralized output feedback control of large-scale nonlinear systems interconnected by unmeasurable states.

Michael T. Frye, Yuanlin Lu, Chunjiang Qian

Proceedings of the 2004 American Control Conference, 2004