Vishwani D. Agrawal

According to our database1, Vishwani D. Agrawal authored at least 303 papers between 1972 and 2021.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2002, "For contributions to testing of digital electronic circuits.".

IEEE Fellow

IEEE Fellow 1986, "For contributions to probabilistic testing techniques for large integrated circuits.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Estimating Operational Age of an Integrated Circuit.
J. Electron. Test., 2021

Defect Characterization and Testing of Skyrmion-Based Logic Circuits.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2020
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures.
J. Electron. Test., 2020

Special Session: Survey of Test Point Insertion for Logic Built-in Self-test.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Message from the Steering Committee Chair.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Machine Intelligence for Efficient Test Pattern Generation.
Proceedings of the IEEE International Test Conference, 2020

2019
Special Session: Delay Fault Testing - Present and Future.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Energy Efficient Power Distribution on Many-Core SoC.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Two-Pattern ∆IDDQ Test for Recycled IC Detection.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Technology Characterization Model and Scaling for Energy Management.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Improved Random Pattern Delay Fault Coverage Using Inversion Test Points.
Proceedings of the 28th IEEE North Atlantic Test Workshop, 2019

Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
Modeling and test generation for combinational hardware Trojans.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2017
Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects.
J. Electron. Test., 2017

Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling.
J. Electron. Test., 2017

2016
Applications of Mixed-Signal Technology in Digital Testing.
J. Electron. Test., 2016

Database Search and ATPG - Interdisciplinary Domains and Algorithms.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Failures Guide Probabilistic Search for a Hard-to-Find Test.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

2015
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests.
J. Electron. Test., 2015

A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing.
J. Electron. Test., 2015

Diagnostic Tests for Pre-bond TSV Defects.
Proceedings of the 28th International Conference on VLSI Design, 2015

Few Good Frequencies for Power-Constrained Test.
Proceedings of the 28th International Conference on VLSI Design, 2015

SoC TAM Design to Minimize Test Application Time.
Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing.
Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

Characterizing Processors for Energy and Performance Management.
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015

Adopting multi-valued logic for reduced pin-count testing.
Proceedings of the 16th Latin-American Test Symposium, 2015

Message from the LATS2015 Chairs.
Proceedings of the 16th Latin-American Test Symposium, 2015

Quest for a quantum search algorithm for testing stuck-at faults in digital circuits.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
A Four-Transistor Level Converter for Dual-Voltage Low-Power Design.
J. Low Power Electron., 2014

Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools.
J. Electron. Test., 2014

A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs.
J. Electron. Test., 2014

A Test Time Theorem and its Applications.
J. Electron. Test., 2014

A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Specification test minimization for given defect level.
Proceedings of the 15th Latin American Test Workshop, 2014

An optimized diagnostic procedure for pre-bond TSV defects.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Energy-Efficient Dual-Voltage Design Using Topological Constraints.
J. Low Power Electron., 2013

Neural Network Guided Spatial Fault Resilience in Array Processors.
J. Electron. Test., 2013

Eliminating the Timing Penalty of Scan.
J. Electron. Test., 2013

Finding best voltage and frequency to shorten power-constrained test time.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Power-aware SoC test optimization through dynamic voltage and frequency scaling.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Defect Diagnosis of Digital Circuits Using Surrogate Faults.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

ATE test time reduction using asynchronous clock period.
Proceedings of the 2013 IEEE International Test Conference, 2013

High sensitivity test signatures for unconventional analog circuit test paradigms.
Proceedings of the 2013 IEEE International Test Conference, 2013

Yield analysis of a novel wafer manipulation method in 3D stacking.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients.
J. Electron. Test., 2012

Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing.
J. Electron. Test., 2012

Diagnostic Test Set Minimization and Full-Response Fault Dictionary.
J. Electron. Test., 2012

Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®.
J. Electron. Test., 2012

Net diagnosis using stuck-at and transition fault models.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Towards spatial fault resilience in array processors.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock.
Proceedings of the 25th International Conference on VLSI Design, 2012

Keynote Talk: A History of the VLSI Design Conference.
Proceedings of the 25th International Conference on VLSI Design, 2012

Power Problems in VLSI Circuit Testing.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Optimal power-constrained SoC test schedules with customizable clock rates.
Proceedings of the IEEE 25th International SOC Conference, 2012

Retiming scan circuit to eliminate timing penalty.
Proceedings of the 13th Latin American Test Workshop, 2012

Impact of process variations on computers used for image processing.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Tailoring Tests for Functional Binning of Integrated Circuits.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply.
J. Low Power Electron., 2011

Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Dynamic scan clock control for test time reduction maintaining peak power limit.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

An efficient test data reduction technique through dynamic pattern mixing across multiple fault models.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

True Minimum Energy Design Using Dual Below-Threshold Supply Voltages.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Reduced complexity test generation algorithms for transition fault diagnosis.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Test and Diagnosis of Analog Circuits Using Moment Generating Functions.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Application of signal and noise theory to digital VLSI testing.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A diagnostic test generation system.
Proceedings of the 2011 IEEE International Test Conference, 2010

Soft error rate determination for nanoscale sequential logic.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A diagnostic test generation system and a coverage metric.
Proceedings of the 15th European Test Symposium, 2010

2009
Variable Input Delay CMOS Logic for Low Power Design.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Output Hazard-Free Transition Delay Fault Test Generation.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Soft Error Rates with Inertial and Logical Masking.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Designing Variation-tolerance in Mixed-signal Components of a System-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Polynomial coefficient based DC testing of non-linear analog circuits.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

On Minimization of Peak Power for Scan Circuit during Test.
Proceedings of the 14th IEEE European Test Symposium, 2009

A Two Phase Approach for Minimal Diagnostic Test Set Generation.
Proceedings of the 14th IEEE European Test Symposium, 2009

Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Single Event Upset: An Embedded Tutorial.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Built-in Self-Calibration of On-chip DAC and ADC.
Proceedings of the 2008 IEEE International Test Conference, 2008

A tutorial on test power.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Graphical I<sub>DDQ</sub> Signatures Reduce Defect Level and Yield Loss.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Delay Test Quality Evaluation Using Bounded Gate Delays.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Spectral RTL Test Generation for Microprocessors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Statistical Leakage and Timing Optimization for Submicron Process Variation.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Reduced Complexity Algorithm for Minimizing N-Detect Tests.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

SPARTAN: a spectral and information theoretic approach to partial-scan.
Proceedings of the 2007 IEEE International Test Conference, 2007

Delay fault simulation with bounded gate delay mode.
Proceedings of the 2007 IEEE International Test Conference, 2007

Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis.
Proceedings of the 2007 IEEE International Test Conference, 2007

2006
Transistor Sizing of Logic Gates to Maximize Input Delay Variability.
J. Low Power Electron., 2006

CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff.
J. Low Power Electron., 2006

Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Fault Coverage Estimation for Non-Random Functional Input Sequences.
Proceedings of the 2006 IEEE International Test Conference, 2006

Input-specific dynamic power optimization for VLSI circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005
Combinational automatic test pattern generation for acyclic sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Design of Variable Input Delay Gates for Low Dynamic Power Circuits.
Proceedings of the Integrated Circuit and System Design, 2005

Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V<sub>th</sub> Assignment and Path Balancing.
Proceedings of the Integrated Circuit and System Design, 2005

A random access scans architecture to reduce hardware overhead.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Dual-transition glitch filtering in probabilistic waveform power estimation.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Diagnostic and Detection Fault Collapsing for Multiple Output Circuits.
Proceedings of the 2005 Design, 2005

Concurrent Test Generation.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults.
J. Comput. Sci. Technol., 2004

1985 to 1987: My years with D&T.
IEEE Des. Test Comput., 2004

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Tuturial on the Emerging Nanotechnology Devices.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
A test evaluation technique for VLSI circuits using register-transfer level fault modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

A Fault-Independent Transitive Closure Algorithm for Redundancy Identification.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Exclusive Test and its Applications to Fault Diagnosis.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Fault Collapsing via Functional Dominance.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
State and Fault Information for Compaction-Based Test Generation.
J. Electron. Test., 2002

Multiple Faults: Modeling, Simulation and Test.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Electronic Testing for SOC Designers (Tutorial Abstract).
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A New Transitive Closure Algorithm with Application to Redundancy Identification.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Combinational test generation for various classes of acyclic sequential circuits.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Efficient spectral techniques for sequential ATPG.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Improving path delay testability of sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Path delay fault simulation of sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2000

False-Path Removal Using Delay Fault Simulation.
J. Electron. Test., 2000

Choice of Tests for Logic Verification and Equivalence Checking.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Register-transfer level fault modeling and test evaluation techniques for VLSI circuits.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Reducing the Complexity of Defect Level Modeling Using the Clustering Effect.
Proceedings of the 2000 Design, 2000

Compaction-based test generation using state and fault information.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Collaboration between Industry and Academia in Test Research.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Testing in the Fourth Dimension.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A testability metric for path delay faults and its application.
Proceedings of ASP-DAC 2000, 2000

1999
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Complete Characterization of Path Delay Faults through Stuck-at Faults.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Test Generator for Segment Delay Faults.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Panel: Increasing test coverage in a VLSI desgin course.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
A rated-clock test method for path delay faults.
IEEE Trans. Very Large Scale Integr. Syst., 1998

A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

The path-status graph with application to delay fault simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Deriving Logic Systems for Path Delay Test Generation.
IEEE Trans. Computers, 1998

Numerical computation of characteristic polynomials of Boolean functions and its applications.
Numer. Algorithms, 1998

Design of mixed-signal systems for testability.
Integr., 1998

Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.
J. Electron. Test., 1998

Editorial.
Des. Autom. Embed. Syst., 1998

On Delay-Untestable Paths and Stuck-Fault Redundancy.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Path Delay Testing: Variable-Clock Versus Rated-Clock.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Tutorial: Delay Fault Models and Coverage.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Mixed-Signal Test.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Optimizing Logic Design Using Boolean Transforms.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A non-enumerative path delay fault simulator for sequential circuits.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Mutually Disjoint Signals and Probability Calculation in Digital Circuits.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

False-Path Removal Using Delay Fault Simulation.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Scheduling tests for VLSI systems under power constraints.
IEEE Trans. Very Large Scale Integr. Syst., 1997

Improving a nonenumerative method to estimate path delay fault coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Redundancy removal and test generation for circuits with non-Boolean primitives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

On variable clock methods for path delay testing of sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests.
J. Electron. Test., 1997

Power Dissipation During Testing: Should We Worry About it?
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Low-Power Design by Hazard Filtering.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Effective Path Selection for Delay Fault Testing of Sequential Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Algorithms for Switch Level Delay Fault Simulation.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Fast identification of untestable delay faults using implications.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Functional test generation for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995 Asian Test Symposium carves a niche.
IEEE Des. Test Comput., 1996

Segment delay faults: a new fault model.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Statistical path delay fault coverage estimation for synchronous sequential circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

On test coverage of path delay faults.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Improving accuracy in path delay fault coverage estimation.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Parallel concurrent path-delay fault simulation using single-input change patterns.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Design for high-speed testability of stuck-at faults.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Characteristic polynomial method for verification and test of combinational circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Science, Technology, and the Indian Society.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

An Exact Non-Enumerative Fault Simulator for Path-Delay Faults.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Synthesis of Self-Testing Finite State Machines from High-Level Specifications.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

SIGMA: a simulator for segment delay faults.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Improving Circuit Testability by Clock Control.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Redundancy Identification Using Transitive Closure.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
A partition and resynthesis approach to testable design of large circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Test function embedding algorithms with application to interconnected finite state machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Fault coverage estimation by test vector sampling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Energy models for delay testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Combinational ATPG theorems for identifying untestable faults in sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Test Generation for Path Delay Faults Using Binary Decision Diagrams.
IEEE Trans. Computers, 1995

An exact algorithm for selecting partial scan flip-flops.
J. Electron. Test., 1995

Editorial - Special issue on partial scan design.
J. Electron. Test., 1995

Simulation of at-speed tests for stuck-at faults.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Functional test generation for non-scan sequential circuits.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

An asynchronous algorithm for sequential circuit test generation on a network of workstations.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

An efficient automatic test generation system for path delay faults in combinational circuits.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Statistical methods for delay fault coverage analysis.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Robust testing for stuck-at faults.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

High-Performance Circuit Testing with Slow-Speed Testers.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

An adaptive distributed algorithm for sequential circuit test generation.
Proceedings of the Proceedings EURO-DAC'95, 1995

Functional test generation for path delay faults.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Sequential logic path delay test generation by symbolic analysis.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Panel: New Research Problems in the Emerging Test Technology.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
Energy minimization and design for testability.
J. Electron. Test., 1994

A tale of two designs: the cheapest and the most economic.
J. Electron. Test., 1994

FACTS: fault coverage estimation by test vector sampling.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Improved Deductive Fault Simulator.
Proceedings of the Seventh International Conference on VLSI Design, 1994

A Test Function Architecture for Interconnected Finite State Machines.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Power Constraint Scheduling of Tests.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Delay independent initialization of sequential circuits.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

An Efficient Path Delay Fault Coverage Estimator.
Proceedings of the 31st Conference on Design Automation, 1994

Concurrent and comparative discrete event simulation.
Kluwer, ISBN: 978-0-7923-9411-2, 1994

1993
Accurate computation of field reject ratio based on fault latency.
IEEE Trans. Very Large Scale Integr. Syst., 1993

Path delay fault simulation of sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1993

A transitive closure algorithm for test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Finite state machine synthesis with fault tolerant test function.
J. Electron. Test., 1993

The optimistic update theorem for path delay testing in sequential circuits.
J. Electron. Test., 1993

A Tutorial on Built-In Self-Test, Part 2: Applications.
IEEE Des. Test Comput., 1993

A Tutorial on Built-in Self-Test. I. Principles.
IEEE Des. Test Comput., 1993

Generating Tests for Delay Faults in Nonscan Circuits.
IEEE Des. Test Comput., 1993

Partial scan testing with single clock control.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

A Path Delay Fault Simulator for Sequential Circuits.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A Synthesis Approach to Design for Testability.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Generation of Compact Delay Tests by Multiple-Path Activation.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Test Pattern Generation for Sequential Circuits on a Network of Workstations.
Proceedings of the Second International Symposium on High Performance Distributed Computing, 1993

Clock partitioning for testability.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

Delay fault testability evaluation through timing simulation.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

Logic systems for path delay test generation.
Proceedings of the European Design Automation Conference 1993, 1993

Design for Testability for Path Delay faults in Sequential Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Sequential Circuit Test Generation on a Distributed System.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems.
IEEE Trans. Parallel Distributed Syst., 1992

Initializability Consideration in Sequential Machine Synthesis.
IEEE Trans. Computers, 1992

The Comparative and Concurrent Simulation of discrete-event experiments.
J. Electron. Test., 1992

Multiple fault detection in two-level multi-output circuits.
J. Electron. Test., 1992

Functional Test Generation for Sequential Circuits.
Proceedings of the Fifth International Conference on VLSI Design, 1992

A New Method for Generating Tests for Delay Faults in Non-Scan Circuits.
Proceedings of the Fifth International Conference on VLSI Design, 1992

Finite State Machine Testing Based on Growth and Dissappearance Faults.
Proceedings of the Digest of Papers: FTCS-22, 1992

DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits.
Proceedings of the conference on European design automation, 1992

Delay Fault Models and Test Generation for Random Logic Sequential Circuits.
Proceedings of the 29th Design Automation Conference, 1992

Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions.
Proceedings of the 29th Design Automation Conference, 1992

1991
Estimating the Quality of Manufactured Digital Sequential Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Stafan Algorithms for MOS Circuits.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Design and Test-The Two Sides of a Coin.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

A Transitive Closure Based Algorithm for Test Generation.
Proceedings of the 28th Design Automation Conference, 1991

1990
Toward massively parallel automatic test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

A Statistical Theory of Digital Circuit Testability.
IEEE Trans. Computers, 1990

A Simulation-Based Method for Generating Tests for Sequential Circuits.
IEEE Trans. Computers, 1990

A Partial Scan Method for Sequential Circuits with Feedback.
IEEE Trans. Computers, 1990

Finite state machine synthesis with embedded test function.
J. Electron. Test., 1990

Neural Net and Boolean Satisfiability Models of Logic Circuits.
IEEE Des. Test Comput., 1990

Fault Sampling Revisited.
IEEE Des. Test Comput., 1990

Performance estimation in a massively parallel system.
Proceedings of the Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, 1990

An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Logic Simulation and Parallel Processing.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Polynomial time solvable fault detection problems.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

An architecture for synthesis of testable finite state machines.
Proceedings of the European Design Automation Conference, 1990

An Entropy Measure for the Complexity of Multi-Output Boolean Functions.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Automatic Test Generation Using Quadratic 0-1 Programming.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Test Function Specification in Synthesis.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
A directed search method for test generation using a concurrent simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

A new model for computation of probabilistic testability in combinational circuits.
Integr., 1989

Fault Simulation in a Pipelined Multiprocessor System.
Proceedings of the Proceedings International Test Conference 1989, 1989

Design of sequential machines for efficient test generation.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

State assignment for initializable synthesis (gate level analysis).
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

An economical scan design for sequential logic test generation.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988
Designing circuits with partial scan.
IEEE Des. Test, 1988

Automatic test generation using neural networks.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

A sequential circuit test generation using threshold-value simulation.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

Contest: A Concurrent Test Generator for Sequential Circuits.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1986
Deterministic Versus Random Testing.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
Modeling and Test Generation Algorithms for MOS Circuits.
IEEE Trans. Computers, 1985

Statistical Fault Analysis.
IEEE Des. Test, 1985

STAFAN Takes a Middle Course.
Proceedings of the Proceedings International Test Conference 1985, 1985

Multiple output minimization.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

VLSI design process.
Proceedings of the 13th ACM Annual Conference on Computer Science, 1985

1984
Characterizing the LSI Yield Equation from Wafer Test Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

Will Testability Analysis Replace Fault Simulation ?
Proceedings of the Proceedings International Test Conference 1984, 1984

A gate level model for CMOS combinational logic circuits with application to fault detection.
Proceedings of the 21st Design Automation Conference, 1984

STAFAN: An alternative to fault simulation.
Proceedings of the 21st Design Automation Conference, 1984

Chip layout optimization using critical path weighting.
Proceedings of the 21st Design Automation Conference, 1984

1983
Test generation for MOS circuits using D-algorithm.
Proceedings of the 20th Design Automation Conference, 1983

1982
Testability Measures : What Do They Tell Us ?
Proceedings of the Proceedings International Test Conference 1982, 1982

Synchronous path analysis in MOS circuit simulator.
Proceedings of the 19th Design Automation Conference, 1982

1981
An Information Theoretic Approach to Digital Fault Testing.
IEEE Trans. Computers, 1981

Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation.
Proceedings of the Proceedings International Test Conference 1981, 1981

LSI product quality and fault coverage.
Proceedings of the 18th Design Automation Conference, 1981

1980
A mixed-mode simulator.
Proceedings of the 17th Design Automation Conference, 1980

1979
Author's Reply.
IEEE Trans. Computers, 1979

Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays".
IEEE Trans. Computers, 1979

1978
When to Use Random Testing.
IEEE Trans. Computers, 1978

1976
On Monte Carlo Testing of Logic Tree Networks.
IEEE Trans. Computers, 1976

1975
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks.
IEEE Trans. Computers, 1975

1972
An Automatic Test Generation System for Illiac IV Logic Boards.
IEEE Trans. Computers, 1972


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