Yuanmiao Lin

Orcid: 0009-0005-9106-5989

According to our database1, Yuanmiao Lin authored at least 8 papers between 2025 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Efficient FPGA Acceleration for 4-bit CNNs via Quantization-Induced Structured Sparsity and LUT-Based Multiplication.
IEEE Trans. Very Large Scale Integr. Syst., May, 2026

An efficient DSP packing framework for FPGA-based mixed-precision DCNN processor.
J. Syst. Archit., 2026

2025
A Precision-Scalable Accelerator with Sign-Magnitude Representation and Dual Adder Trees.
ACM Trans. Embed. Comput. Syst., November, 2025

An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

An FPGA-based bit-level weight sparsity and mixed-bit accelerator for neural networks.
J. Syst. Archit., 2025

A precision-scalable sparse CNN accelerator with fine-grained mixed bitwidth configurability.
IEICE Electron. Express, 2025

A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator.
IEEE Comput. Archit. Lett., 2025

A Multiple-Aspect Optimal CNN Accelerator in Top1 Accuracy, Performance, and Power Efficiency.
IEEE Comput. Archit. Lett., 2025


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