Xueming Li

According to our database, Xueming Li authored at least 15 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Efficient FPGA Acceleration for 4-bit CNNs via Quantization-Induced Structured Sparsity and LUT-Based Multiplication.

Yuanmiao Lin, Peng Zhang, Zijian Zhang, Xueming Li, Hongmin Huang, Ruidian Zhan, Xianghong Hu, Shuting Cai, Xiaoming Xiong

IEEE Trans. Very Large Scale Integr. Syst., May, 2026

An efficient DSP packing framework for FPGA-based mixed-precision DCNN processor.

Xueming Li, Jinhui Pan, Hongmin Huang, Yuanmiao Lin, Xianghong Hu, Shuting Cai, Xiaoming Xiong

J. Syst. Archit., 2026

2025

A Precision-Scalable Accelerator with Sign-Magnitude Representation and Dual Adder Trees.

Xianghong Hu, Chaoming Yang, Xueming Li, Rongfeng Li, Yuanmiao Lin, Shansen Fu, Hongmin Huang, Shuting Cai, Xiaoming Xiong

ACM Trans. Embed. Comput. Syst., November, 2025

An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization.

Yuanmiao Lin, Zhaozhang Feng, Xueming Li, Hongmin Huang, Ruidian Zhan, Xianghong Hu, Shuting Cai, Xiaoming Xiong

IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

An FPGA-based bit-level weight sparsity and mixed-bit accelerator for neural networks.

Xianghong Hu, Shansen Fu, Yuanmiao Lin, Xueming Li, Chaoming Yang, Rongfeng Li, Hongmin Huang, Shuting Cai, Xiaoming Xiong

J. Syst. Archit., 2025

A High-Efficiency CNN Accelerator With Mixed Low-Precision Quantization.

Xianghong Hu, Jinhui Pan, Yue Ding, Wenji Huang, Zhejun Zheng, Xueming Li, Hongmin Huang, Xiaoming Xiong

IET Circuits Devices Syst., 2025

A precision-scalable sparse CNN accelerator with fine-grained mixed bitwidth configurability.

Rongfeng Li, Xueming Li, Chaoming Yang, Xianghong Hu, Yuanmiao Lin, Shansen Fu, Hongmin Huang, Shuting Cai, Xiaoming Xiong

IEICE Electron. Express, 2025

A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator.

Yuanmiao Lin, Shansen Fu, Xueming Li, Chaoming Yang, Rongfeng Li, Hongmin Huang, Xianghong Hu, Shuting Cai, Xiaoming Xiong

IEEE Comput. Archit. Lett., 2025

A Multiple-Aspect Optimal CNN Accelerator in Top1 Accuracy, Performance, and Power Efficiency.

Xianghong Hu, Yuanmiao Lin, Xueming Li, Ruidian Zhan, Jie Cao, Dayong Zhu, Shuting Cai, Xin Zheng, Xiaoming Xiong

IEEE Comput. Archit. Lett., 2025

2023

High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System.

Xianghong Hu, Hongmin Huang, Xueming Li, Xin Zheng, Qinyuan Ren, Jingyu He, Xiaoming Xiong

ACM Trans. Embed. Comput. Syst., November, 2023

2022

TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization.

Xianghong Hu, Xueming Li, Hongmin Huang, Xin Zheng, Xiaoming Xiong

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A hardware-efficient computing engine for FPGA-based deep convolutional neural network accelerator.

Xueming Li, Hongmin Huang, Taosheng Chen, Huaien Gao, Xianghong Hu, Xiaoming Xiong

Microelectron. J., 2022

An efficient loop tiling framework for convolutional neural network inference accelerators.

Hongmin Huang, Xianghong Hu, Xueming Li, Xiaoming Xiong

IET Circuits Devices Syst., 2022

A high speed processor for elliptic curve cryptography over NIST prime field.

Xianghong Hu, Xueming Li, Xin Zheng, Yuan Liu, Xiaoming Xiong

IET Circuits Devices Syst., 2022

An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs.

Hongmin Huang, Xueming Li, Yadong Qin, Xianghong Hu, Xiaoming Xiong

Proceedings of the HP3C 2022: 6th International Conference on High Performance Compilation, 2022