Yuanyang Xiang

According to our database, Yuanyang Xiang authored at least 6 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

LoopHint: A Compiler-Assisted Loop Branch Predictor for Embedded DSPs.

Yuanyang Xiang, Chen Xu, Ruozhou Xiao, Zhiwei Zhang

Proceedings of the 27th ACM SIGPLAN/SIGBED International Conference on Languages, 2026

Breaking the Local Optima Barrier in Branch Predictor Design Space Exploration: An LLM-Based Initialization Strategy for PSO.

Qingchen Zhai, Chen Xu, Yuanyang Xiang, Yueyue Wang, Weiying Wang, Kunyu Zong, Jingshuai Jiang, Ruozhou Xiao, Zhiwei Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

RTCore: A RISC-V Processor Featuring Nested Hardware Loop Optimization for Real-time Control System.

Qingchen Zhai, Weiying Wang, Yueyue Wang, Yuanyang Xiang, Chen Xu, Kunyu Zong, Ruozhou Xiao, Zhiwei Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025

Instruction Level Parallelism Optimizations in a High-Performance Dual-Issue RISC-V Processor for Real-Time Control Systems.

Qingchen Zhai, Weiying Wang, Yueyue Wang, Yuanyang Xiang, Chen Xu, Kunyu Zong, Ruozhou Xiao, Zhiwei Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Using Greedy-Enhanced Heuristic to Optimize Instruction Scheduling for RISC-V DS.

Chen Xu, Yuanyang Xiang, Qingchen Zhai, Ruozhou Xiao, Zhiwei Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Lightweight RISC-V Multi-Core Interaction Framework For Embedded Real-Time Applications.

Yuanyang Xiang, Chen Xu, Yueyue Wang, Weiying Wang, Qingchen Zhai, Kunyu Zong, Ruozhou Xiao, Zhiwei Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025