Yujun Xie

According to our database, Yujun Xie authored at least 8 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A Low Area-Time ECPM Hardware Accelerator Over Curve25519 on FPGA.

Yujun Xie, Zhaoyang Ren, Jianlang Lu, Yuan Liu

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

2025

Area-Efficient Modular Multiplication on FPGA.

Yujun Xie, Yuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

An Efficient LUT6-Based Montgomery Modular Multiplication Using Radix-16 Booth Method.

Yujun Xie, Yuan Liu

IEEE Trans. Computers, September, 2025

A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves.

Yujun Xie, Riheng Yan, Yuan Liu, Xin Zheng, Shuting Cai, Xiaoming Xiong

IEEE Embed. Syst. Lett., August, 2025

FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA.

Yujun Xie, Yuan Liu, Xin Zheng, Bohan Lan, Dengyun Lei, Dehao Xiang, Shuting Cai, Xiaoming Xiong

IEEE Trans. Computers, January, 2025

NIRECP: An ECC Processor Over 256-Bit NIST Prime Field Using New Iterative Reduction.

Yujun Xie, Riheng Yan, Bohan Lan, Yuan Liu

Int. J. Circuit Theory Appl., 2025

2022

A Dual-Core High-Performance Processor for Elliptic Curve Cryptography in GF(p) Over Generic Weierstrass Curves.

Yujun Xie, Yuan Liu, Xin Zheng, Wenhao Zhu, Junxian Li, Jianzhong Li, Shuting Cai, Xiaoming Xiong

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A high-performance processor for optimal ate pairing computation over Barreto-Naehrig curves.

Yujun Xie, Bin Wang, Lijun Zhang, Xin Zheng, Xiaoling Lin, Xiaoming Xiong, Yuan Liu

IET Circuits Devices Syst., 2022