Zengshi Wang

According to our database, Zengshi Wang authored at least 4 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

DARE: An Irregularity-Tolerant Matrix Processing Unit with a Densifying ISA and Filtered Runahead Execution.

Xin Yang, Xin Fan, Zengshi Wang, Jun Han

CoRR, November, 2025

VLSUMaP: A High-Performance Matrix Processor with Virtually Expanded LSU Boosting HBM Bandwidth Utilization.

Xin Yang, Xinjie Kong, Kaixuan Wang, Xin Fan, Zikang Zhou, Zhuoyuan Yang, Zengshi Wang, Jun Han

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

2024

Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification.

Chao Fu, Zengshi Wang, Jun Han

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

2023

Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System.

Zengshi Wang, Chao Fu, Jun Han

Proceedings of the 15th IEEE International Conference on ASIC, 2023