Zezheng Liu

Orcid: 0009-0009-0677-4975

According to our database1, Zezheng Liu authored at least 16 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur.
IEEE J. Solid State Circuits, June, 2025

A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference.
IEEE J. Solid State Circuits, March, 2025

A Nano-g Fabry-Pérot Damped Accelerometer Featuring All-Metal-Elastic Fiber Optics Technology With 112-dB Dynamic Range.
IEEE Trans. Instrum. Meas., 2025

5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated Jitter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter.
IEEE J. Solid State Circuits, April, 2024

A synthesizable spread spectrum clock generator based on type-II/III fractional-<i>N</i> DPLL.
IEICE Electron. Express, 2024

Two Teachers Are Better Than One: Semi-supervised Elliptical Object Detection by Dual-Teacher Collaborative Guidance.
Proceedings of the 32nd ACM International Conference on Multimedia, MM 2024, Melbourne, VIC, Australia, 28 October 2024, 2024

10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Optimization on Architecture of Time-Sensitive Software-Defined Network.
Proceedings of the Eleventh International Conference on Advanced Cloud and Big Data, 2023

2022
Vegetation Pattern Formation and Transition Caused by Cross-Diffusion in a Modified Vegetation-Sand Model.
Int. J. Bifurc. Chaos, 2022

2021
A 0.25 mm<sup>2</sup> BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
Image quality assessment based on adaptive multiple Skyline query.
Signal Process. Image Commun., 2020


  Loading...