Zhen Hang Jiang

According to our database1, Zhen Hang Jiang authored at least 8 papers between 2016 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2020
Exploiting Bank Conflict-based Side-channel Timing Leakage of GPUs.
ACM Trans. Archit. Code Optim., 2020

MemPoline: Mitigating Memory-based Side-Channel Attacks through Memory Access Obfuscation.
IACR Cryptol. ePrint Arch., 2020

2018
A Timing Side-Channel Attack on a Mobile GPU.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017
Compiler-Assisted Threshold Implementation against Power Analysis Attacks.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A novel cache bank timing attack.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A Novel Side-Channel Timing Attack on GPUs.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Statistical Analysis for Access-Driven Cache Attacks Against AES.
IACR Cryptol. ePrint Arch., 2016

A complete key recovery timing attack on a GPU.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016


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