Yunsi Fei

Orcid: 0000-0002-9930-0868

According to our database1, Yunsi Fei authored at least 132 papers between 2002 and 2023.

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Bibliography

2023
A Guessing Entropy-Based Framework for Deep Learning-Assisted Side-Channel Analysis.
IEEE Trans. Inf. Forensics Secur., 2023

Identification of Stealthy Hardware Trojans through On-Chip Temperature Sensing and an Autoencoder-Based Machine Learning Algorithm.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

VertexSerum: Poisoning Graph Neural Networks for Link Inference.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

Deep-Learning Model Extraction Through Software-Based Power Side-Channel.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

An Energy-Efficient Neural Network Accelerator with Improved Protections Against Fault-Attacks.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

HammerDodger: A Lightweight Defense Framework against RowHammer Attack on DNNs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

EMShepherd: Detecting Adversarial Samples via Side-channel Leakage.
Proceedings of the 2023 ACM Asia Conference on Computer and Communications Security, 2023

2022
Masking Feedforward Neural Networks Against Power Analysis Attacks.
Proc. Priv. Enhancing Technol., 2022

High-Precision Nano-Amp Current Sensor and Obfuscation based Analog Trojan Detection Circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Ran$Net: An Anti-Ransomware Methodology based on Cache Monitoring and Deep Learning.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Protected ECC Still Leaks: A Novel Differential-Bit Side-channel Power Attack on ECDH and Countermeasures.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

A Cross-Platform Cache Timing Attack Framework via Deep Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Large Delay Analog Trojans: A Silent Fabrication-Time Attack Exploiting Analog Modalities.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Introduction to the Special Issue on Emerging Challenges and Solutions in Hardware Security.
ACM J. Emerg. Technol. Comput. Syst., 2021

Sensitive Samples Revisited: Detecting Neural Network Attacks Using Constraint Solvers.
Proceedings of the 9th International Symposium on Symbolic Computation in Software Science, 2021

GPU Overdrive Fault Attacks on Neural Networks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Overdrive Fault Attacks on GPUs.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021

DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Intrinsic Examples: Robust Fingerprinting of Deep Neural Networks.
Proceedings of the 32nd British Machine Vision Conference 2021, 2021

2020
Nacre<sup>*</sup>*Nacre, or mother-of-pearl, is one of nature's remarkable examples of a durable and break-resistant structure.: Durable, Secure and Energy-Efficient Non-Volatile Memory Utilizing Data Versioning.
IEEE Trans. Emerg. Top. Comput., 2020

A Fast and Accurate Guessing Entropy Estimation Algorithm for Full-key Recovery.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Exploiting Bank Conflict-based Side-channel Timing Leakage of GPUs.
ACM Trans. Archit. Code Optim., 2020

MemPoline: Mitigating Memory-based Side-Channel Attacks through Memory Access Obfuscation.
IACR Cryptol. ePrint Arch., 2020

Correlation Power Analysis and Higher-order Masking Implementation of WAGE.
IACR Cryptol. ePrint Arch., 2020

Automatic Detection and Repair of Transition- Based Leakage in Software Binaries.
Proceedings of the Software Verification - 12th International Conference, 2020

An Ultra-low Power and Lower Area Current-Mode based Physically Unclonable Function with less than 100nW Power Consumption and a Native Instability of 0.6875% for IoT Applications.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Stealthy-Shutdown: Practical Remote Power Attacks in Multi - Tenant FPGAs.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

New Passive and Active Attacks on Deep Neural Networks in Medical Applications.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Hardware/Software Obfuscation against Timing Side-channel Attack on a GPU.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Novel GPU Overdrive Fault Attack.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Reverse-Engineering Deep Neural Networks Using Floating-Point Timing Side-Channels.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Efficient Nonprofiling 2nd-Order Power Analysis on Masked Devices Utilizing Multiple Leakage Points.
IEEE Trans. Dependable Secur. Comput., 2019

Comprehensive Side-Channel Power Analysis of XTS-AES.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Side-channel Timing Attack of RSA on a GPU.
ACM Trans. Archit. Code Optim., 2019

Guest Editorial: Special Issue on Hardware Solutions for Cyber Security.
J. Hardw. Syst. Secur., 2019

Evaluating Fault Resiliency of Compressed Deep Neural Networks.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Fault Sneaking Attack: a Stealthy Framework for Misleading Deep Neural Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Algebraic Fault Analysis of SHA-3 Under Relaxed Fault Models.
IEEE Trans. Inf. Forensics Secur., 2018

Power Analysis Attack of an AES GPU Implementation.
J. Hardw. Syst. Secur., 2018

Mission Assurance: Beyond Secure Processing.
Proceedings of the 2018 IEEE International Conference on Software Quality, 2018

A Timing Side-Channel Attack on a Mobile GPU.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

SCADET: a side-channel attack detection tool for tracking prime+probe.
Proceedings of the International Conference on Computer-Aided Design, 2018

Effective simple-power analysis attacks of elliptic curve cryptography on embedded systems.
Proceedings of the International Conference on Computer-Aided Design, 2018

GPU acceleration of RSA is vulnerable to side-channel timing attacks.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
A PHEV Power Management Cyber-Physical System for On-Road Applications.
IEEE Trans. Veh. Technol., 2017

TARS: A Traffic-Adaptive Receiver-Synchronized MAC Protocol for Underwater Sensor Networks.
ACM Trans. Sens. Networks, 2017

Vehicle Speed Prediction by Two-Level Data Driven Models in Vehicular Networks.
IEEE Trans. Intell. Transp. Syst., 2017

Embedded Device Forensics and Security.
ACM Trans. Embed. Comput. Syst., 2017

Differential Fault Analysis of SHA-3 Under Relaxed Fault Models.
J. Hardw. Syst. Secur., 2017

Towards Sound and Optimal Leakage Detection Procedure.
IACR Cryptol. ePrint Arch., 2017

Algebraic Fault Analysis of SHA-3.
IACR Cryptol. ePrint Arch., 2017

Compiler-Assisted Threshold Implementation against Power Analysis Attacks.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A novel cache bank timing attack.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A Novel Side-Channel Timing Attack on GPUs.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Side-channel power analysis of XTS-AES.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
A Unified Metric for Quantifying Information Leakage of Cryptographic Devices under Power Analysis Attacks.
IACR Cryptol. ePrint Arch., 2016

Statistical Analysis for Access-Driven Cache Attacks Against AES.
IACR Cryptol. ePrint Arch., 2016

An Improvement of Both Security and Reliability for Keccak Implementations on Smart Card.
IACR Cryptol. ePrint Arch., 2016

System Clock and Power Supply Cross-Checking for Glitch Detection.
IACR Cryptol. ePrint Arch., 2016

Differential Fault Analysis of SHA3-224 and SHA3-256.
IACR Cryptol. ePrint Arch., 2016

Faulty Clock Detection for Crypto Circuits Against Differential Fault Analysis Attack.
IACR Cryptol. ePrint Arch., 2016

DAP-MAC: A delay-aware probability-based MAC protocol for underwater acoustic sensor networks.
Ad Hoc Networks, 2016

SMARP: A Stochastic MAC Protocol with Randomized Power Control for Underwater Sensor Networks.
Proceedings of the 13th Annual IEEE International Conference on Sensing, 2016

A complete key recovery timing attack on a GPU.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Concurrent Error Detection for Reliable SHA-3 Design.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Smart Home in Smart Microgrid: A Cost-Effective Energy Ecosystem With Intelligent Hierarchical Agents.
IEEE Trans. Smart Grid, 2015

A statistics-based success rate model for DPA and CPA.
J. Cryptogr. Eng., 2015

Towards Secure Cryptographic Software Implementation Against Side-Channel Power Analysis Attacks.
IACR Cryptol. ePrint Arch., 2015

Side-Channel Analysis of MAC-Keccak Hardware Implementations.
IACR Cryptol. ePrint Arch., 2015

Guest Editorial: Special Section on Embedded System Security.
IEEE Embed. Syst. Lett., 2015

Traffic and vehicle speed prediction with neural network and Hidden Markov model in vehicular networks.
Proceedings of the 2015 IEEE Intelligent Vehicles Symposium, 2015

A delay-aware probability-based MAC protocol for underwater acoustic sensor networks.
Proceedings of the International Conference on Computing, Networking and Communications, 2015

Side-channel power analysis of a GPU AES implementation.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Leakage evaluation on power balance countermeasure against side-channel attack on FPGAs.
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015

Efficient 2nd-order power analysis on masked devices utilizing multiple leakage.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Balance power leakage to fight against side-channel analysis at gate level in FPGAs.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Side-channel Power Analysis of Different Protection Schemes Against Fault Attacks on AES.
IACR Cryptol. ePrint Arch., 2014

Power Analysis Attack on Hardware Implementation of MAC-Keccak on FPGAs.
IACR Cryptol. ePrint Arch., 2014

A Statistics-based Fundamental Model for Side-channel Attack Analysis.
IACR Cryptol. ePrint Arch., 2014

A Statistical Model for Higher Order DPA on Masked Devices.
IACR Cryptol. ePrint Arch., 2014

HiTS: A High Throughput Memory Scheduling Scheme to Mitigate Denial-of-Service Attacks in Multi-core Systems.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

On-road PHEV power management with hierarchical strategies in vehicular networks.
Proceedings of the 2014 IEEE Intelligent Vehicles Symposium Proceedings, 2014

Scalable and efficient implementation of correlation power analysis using graphics processing units (GPUs).
Proceedings of the HASP 2014, 2014

HATI: Hardware Assisted Thread Isolation for Concurrent C/C++ Programs.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013
Leveraging speculative architectures for runtime program validation.
ACM Trans. Embed. Comput. Syst., 2013

DSH-MAC: Medium Access Control based on Decoupled and Suppressed Handshaking for long-delay Underwater Acoustic Sensor Networks.
Proceedings of the 38th Annual IEEE Conference on Local Computer Networks, 2013

Decentralized scheduling of PEV on-street parking and charging for smart grid reactive power compensation.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2013

Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking.
Proceedings of the HASP 2013, 2013

An adaptive routing protocol based on connectivity prediction for underwater disruption tolerant networks.
Proceedings of the 2013 IEEE Global Communications Conference, 2013

2012
Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Hardware/Software Cooperative Custom Register Binding Approach for Register Spill Elimination in Application-Specific Instruction Set Processors.
ACM Trans. Design Autom. Electr. Syst., 2012

Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design.
ACM Trans. Design Autom. Electr. Syst., 2012

MURAO: A multi-level routing protocol for acoustic-optical hybrid underwater wireless sensor networks.
Proceedings of the 9th Annual IEEE Communications Society Conference on Sensor, 2012

Designing and implementing a Malicious 8051 processor.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

A Statistical Model for DPA with Novel Algorithmic Confusion Analysis.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

Static secure page allocation for light-weight dynamic information flow tracking.
Proceedings of the 15th International Conference on Compilers, 2012

2011
Algorithmic collision analysis for evaluating cryptographic systems and side-channel attacks.
Proceedings of the HOST 2011, 2011

Adaptive Extended Min-Sum Algorithm for Nonbinary LDPC Decoding.
Proceedings of the Global Communications Conference, 2011

2010
Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-Set Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Register File Partitioning and Compiler Support for Reducing Embedded Processor Power Consumption.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Register file partitioning and recompilation for register file power reduction.
ACM Trans. Design Autom. Electr. Syst., 2010

QELAR: A Machine-Learning-Based Adaptive Routing Protocol for Energy-Efficient and Lifetime-Extended Underwater Sensor Networks.
IEEE Trans. Mob. Comput., 2010

An Adaptive and Energy-efficient Routing Protocol Based on Machine Learning for Underwater Delay Tolerant Networks.
Proceedings of the MASCOTS 2010, 2010

Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

A novel multi-objective instruction synthesis flow for application-specific instruction set processors.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Orchestrating Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency.
IEEE Trans. Computers, 2009

A Hierarchical Design of an Application-specific Instruction Set Processor for High-throughput FFT.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Design of an application-specific instruction set processor for high-throughput and scalable FFT.
Proceedings of the Design, Automation and Test in Europe, 2009

PIFT: efficient dynamic information flow tracking using secure page allocation.
Proceedings of the 4th Workshop on Embedded Systems Security, 2009

2008
An energy-aware framework for dynamic software management in mobile computing systems.
ACM Trans. Embed. Comput. Syst., 2008

Thermal-aware Design Considerations for Application-Specific Instruction Set Processor.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

QELAR: A Q-learning-based Energy-Efficient and Lifetime-Aware Routing Protocol for Underwater Sensor Networks.
Proceedings of the 2008 IEEE International Performance, 2008

Leveraging speculative architectures for run-time program validation.
Proceedings of the 26th International Conference on Computer Design, 2008

Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency.
Proceedings of the Design, Automation and Test in Europe, 2008

An efficient digital circuit for implementing Sequence Alignment algorithm in an extended processor.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Reducing power consumption of embedded processors through register file partitioning and compiler support.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
Energy-optimizing source code transformations for operating system-driven embedded software.
ACM Trans. Embed. Comput. Syst., 2007

Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors.
Proceedings of the 25th International Conference on Computer Design, 2007

Utilizing custom registers in application-specific instruction set processors for register spills elimination.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Microarchitectural support for program code integrity monitoring in application-specific instruction set processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005
Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip.
Int. J. Embed. Syst., 2005

2004
Register binding-based RTL power management for control-flow intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A hybrid energy-estimation technique for extensible processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Energy-Optimizing Source Code Transformations for OS-driven Embedded Software.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers.
Proceedings of the 12th International Workshop on Modeling, 2004

2003
A comprehensive high-level synthesis system for control-flow intensive behaviors.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Energy Estimation for Extensible Processors.
Proceedings of the 2003 Design, 2003

2002
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002


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