Zhi Li
Orcid: 0009-0000-5529-1421Affiliations:
- Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China
According to our database1,
Zhi Li
authored at least 16 papers
between 2022 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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Bibliography
2025
Accelerating Unstructured Sparse DNNs via Multilevel Partial Sum Reduction and PE Array-Level Load Balancing.
IEEE Trans. Very Large Scale Integr. Syst., August, 2025
IEEE Trans. Circuits Syst. II Express Briefs, August, 2025
ITP-PAD: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation Detection.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2025
A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit.
IEEE Trans. Very Large Scale Integr. Syst., February, 2025
Erratum: A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits [IEICE Electronics Express Vol. 20 (2023) No. 11 pp. 20230145].
IEICE Electron. Express, 2025
AO-EDC: An Accuracy-Oriented Error Detection and Correction Scheme for DVFS System Based on Propagation Detection at Half-Path Points.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A 230-nA Quiescent Current and Enhanced Transient Performance DC-DC Converter with Suppressed Under/Overshoot for IoT SoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
A dynamic voltage scaling circuit design based on critical path replica and time warning techniques.
IEICE Electron. Express, 2024
An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS.
IEEE Access, 2024
Proceedings of the IEEE International Conference on Integrated Circuits, 2024
2023
A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application.
IEICE Electron. Express, December, 2023
A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM.
IEICE Electron. Express, 2023
A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits.
IEICE Electron. Express, 2023
2022
A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture.
IEICE Electron. Express, 2022
IEICE Electron. Express, 2022