Zhichuan Guo

According to our database, Zhichuan Guo authored at least 19 papers between 2012 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

TRNIC: A High-Performance RDMA NIC with Triple-Table Bitmap for Efficient Out-of-Order Packet Reordering in Multipath Transmission.

Mengting Zhang, Zhichuan Guo, Yipeng Pan, Jiandong Ma, Shining Sun

IEICE Trans. Commun., 2026

GCCache: A Non-blocking and Low-latency General-purpose Context Cache Design for RDMA NICs.

Zhixiang Zhao, Zhichuan Guo, Mangu Song, Zhiyuan Ling

Proceedings of the 27th International Conference on Advanced Communications Technology, 2026

FRAB-MAC: A Reliable Adaptive Broadcast MAC Protocol for Mobile UACNs.

Bo Pang, Zhichuan Guo, Yating Liu

Proceedings of the 27th International Conference on Advanced Communications Technology, 2026

2025

RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks.

Yiwei Chang, Zhichuan Guo

IEEE Trans. Very Large Scale Integr. Syst., January, 2025

Fuzzy-Based Deterministic Routing With Probabilistic Flooding in Underwater Acoustic Sensor Networks.

Bo Pang, Zhichuan Guo, Yating Liu

IEEE Internet Things J., 2025

FPGA-Accelerated VXLAN Chaining for Partially Reconfigurable VNFs in Heterogeneous Data Centers.

Yiwei Chang, Zhichuan Guo

IEICE Trans. Commun., 2025

RoSR: A Novel Selective Retransmission FPGA Architecture for RDMA NICs.

Mengting Zhang, Zhichuan Guo, Shining Sun

IEEE Comput. Archit. Lett., 2025

2024

An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches.

Xiaoyong Song, Zhichuan Guo

IEEE Trans. Very Large Scale Integr. Syst., November, 2024

Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA.

Xiaoyong Song, Zhichuan Guo

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

High-Throughput Exact Matching Implementation on FPGA with Shared Rule Tables Among Parallel Pipelines.

Xiaoyong Song, Zhichuan Guo, Xinshuo Wang, Mangu Song

IEICE Trans. Commun., 2024

FPGA-based implementation of consistent flow configuration system for software-defined networking.

Yiwei Chang, Zhichuan Guo, Yan Jiang

IEICE Electron. Express, 2024

2023

High Performance Network Virtualization Architecture on FPGA SmartNIC.

Ke Wang, Yiwei Chang, Zhichuan Guo

IEICE Trans. Commun., June, 2023

2022

FGLB: A fine-grained hardware intra-server load balancer based on 100 G FPGA SmartNIC.

Xiaoying Huang, Zhichuan Guo, Mangu Song

Int. J. Netw. Manag., 2022

2021

A Multifunctional Full-Packet Capture and Network Measurement System Supporting Nanosecond Timestamp and Real-Time Analysis.

Luchao Han, Zhichuan Guo, Xiaoying Huang, Xuewen Zeng

IEEE Trans. Instrum. Meas., 2021

Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture.

Xiaoying Huang, Zhichuan Guo, Mangu Song, Xuewen Zeng

IET Comput. Digit. Tech., 2021

2020

Malware Traffic Classification Based on Recurrence Quantification Analysis.

Zheng-Zhi Tang, Xuewen Zeng, Zhichuan Guo, Mangu Song

Int. J. Netw. Secur., 2020

High-Performance Implementation of Dynamically Configurable Load Balancing Engine on FPGA.

Jun Zhao, Zhichuan Guo, Xuewen Zeng, Mangu Song

IEEE Commun. Mag., 2020

2019

High Throughput Implementation of SMS4 on FPGA.

Jun Zhao, Zhichuan Guo, Xuewen Zeng

IEEE Access, 2019

2012

Efficient information hiding in H.264/AVC video coding.

Ke Liao, Shiguo Lian, Zhichuan Guo, Jinlin Wang

Telecommun. Syst., 2012