Zhichuan Guo
Orcid: 0000-0003-2489-9949
According to our database1,
Zhichuan Guo
authored at least 9 papers
between 2012 and 2024.
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Bibliography
2024
Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
2023
IEICE Trans. Commun., June, 2023
2022
FGLB: A fine-grained hardware intra-server load balancer based on 100 G FPGA SmartNIC.
Int. J. Netw. Manag., 2022
2021
A Multifunctional Full-Packet Capture and Network Measurement System Supporting Nanosecond Timestamp and Real-Time Analysis.
IEEE Trans. Instrum. Meas., 2021
IET Comput. Digit. Tech., 2021
2020
Int. J. Netw. Secur., 2020
High-Performance Implementation of Dynamically Configurable Load Balancing Engine on FPGA.
IEEE Commun. Mag., 2020
2019
2012