Zhiheng Cao

According to our database1, Zhiheng Cao authored at least 9 papers between 2005 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2009
A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2009

2008
A 2.7-mW 2-MHz Continuous-Time ΣΔ Modulator With a Hybrid Active-Passive Loop Filter.
IEEE J. Solid State Circuits, 2008

A 0.4 ps-RMS-Jitter 1-3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification.
IEEE J. Solid State Circuits, 2008

A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 14 mW 2.5 MS/s 14 bit ΣΔ Modulator Using Split-Path Pseudo-Differential Amplifiers.
IEEE J. Solid State Circuits, 2007

2006
A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop Filter.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode Amplifiers.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A digital background calibration method for mash /spl Sigma/-/spl Delta/ modulators by using coefficient estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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