Shouli Yan

According to our database1, Shouli Yan authored at least 28 papers between 2000 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012
A Mixed Signal (Analog-Digital) Integrator Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010
A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009
A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2009

2008
A Robust and Scalable Constant- g<sub>m</sub> Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 2.7-mW 2-MHz Continuous-Time ΣΔ Modulator With a Hybrid Active-Passive Loop Filter.
IEEE J. Solid State Circuits, 2008

A 0.4 ps-RMS-Jitter 1-3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification.
IEEE J. Solid State Circuits, 2008

A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Constant- g<sub>m</sub> Constant-Slew-Rate Rail-to-Rail Input Stage With Static Feedback and Dynamic Current Steering for VLSI Cell Libraries.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 14 mW 2.5 MS/s 14 bit ΣΔ Modulator Using Split-Path Pseudo-Differential Amplifiers.
IEEE J. Solid State Circuits, 2007

A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
An improved frequency and phase synthesis architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A low power 1.1 MHz CMOS continuous-time delta-sigma modulator with active-passive loop filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop Filter.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode Amplifiers.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Feedforward reversed nested Miller compensation techniques for three-stage amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Constant-g/sub m/ techniques for rail-to-rail CMOS amplifier input stages: a comparative study.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A constant-g/sub m/ rail-to-rail op amp input stage using dynamic current scaling technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Novel and robust constant-g/sub m/ technique for rail-to-rail CMOS amplifier input stages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A new ratio-independent A/D conversion technique for high-resolution pipeline A/D converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A digital background calibration method for mash /spl Sigma/-/spl Delta/ modulators by using coefficient estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An RC time constant auto-tuning structure for high linearity continuous-time ΣΔ modulators and active filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
An auto-tuning structure for continuous time sigma-delta AD converter and high precision filters.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000
A programmable rail-to-rail constant-g<sub>m</sub> input structure for LV amplifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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