Ziang Ge

According to our database, Ziang Ge authored at least 2 papers in 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Inductance-aware Clock Network Synthesis Considering Hierarchical Interconnects in 3D ICs.

Jindong Zhou, Ziang Ge, Chenbo Xi, Pingqiang Zhou

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

Clock-Wirelength-Driven Detailed Placement.

Ziang Ge, Yikai Liu, Jindong Zhou, Pingqiang Zhou

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025