Pingqiang Zhou

Orcid: 0000-0001-9515-9302

According to our database1, Pingqiang Zhou authored at least 58 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022).
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Analysis and Design of Precision-Scalable Computation Array for Efficient Neural Radiance Field Rendering.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

Fast and Accurate NoC Latency Estimation for Application-Specific Traffics via Machine Learning.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

Machine Learning-Based Device Modeling and Performance Optimization for FinFETs.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

A Mapping Method Tolerating SAF and Variation for Memristor Crossbar Array Based Neural Network Inference on Edge Devices.
ACM J. Emerg. Technol. Comput. Syst., April, 2023

The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs.
Integr., 2023

Exploring Remote Power Attacks Targeting Parallel Data Encryption On Multi-Tenant FPGAs.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Speed- and Energy-Driven Holistic Training Framework for Sparse CNN Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Full-Chip Voltage Prediction via Graph Attention Based Neural Networks.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Systolic Array with Activation Stationary Dataflow for Deep Fully-Connected Networks.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
ICARUS: A Specialized Architecture for Neural Radiance Fields Rendering.
ACM Trans. Graph., 2022

Defending against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit-plane Slicing.
ACM J. Emerg. Technol. Comput. Syst., 2022

ICARUS: A Lightweight Neural Plenoptic Rendering Architecture.
CoRR, 2022

An RRAM-based Neural Radiance Field Processor.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Two-Stage Energy Efficiency Optimization of Switched-Capacitor Converters for IoT Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Thermal-Aware Layout Optimization and Mapping Methods for Resistive Neuromorphic Engines.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

SME: A Systolic Multiply-accumulate Engine for MLP-based Neural Network.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

An Energy Efficient Precision Scalable Computation Array for Neural Radiance Field Accelerator.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
Tolerating Stuck-at Fault and Variation in Resistive Edge Inference Engine via Weight Mapping.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Detecting Adversarial Examples Utilizing Pixel Value Diversity.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

Efficient Techniques for Extending Service Time for Memristor-based Neural Networks.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020
How Secure Is Split Manufacturing in Preventing Hardware Trojan?
ACM Trans. Design Autom. Electr. Syst., 2020

Tensor Train Random Projection.
CoRR, 2020

Early-Stage Planning of Switched-Capacitor Converters in a Heterogeneous Chip.
IEEE Access, 2020

Defending Against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit Plane Slicing.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

2019
Dependable Visual Light-Based Indoor Localization with Automatic Anomaly Detection for Location-Based Service of Mobile Cyber-Physical Systems.
ACM Trans. Cyber Phys. Syst., 2019

A Cross-Layer Framework for Temporal Power and Supply Noise Prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Run-time demand estimation and modulation of on-chip decaps at system level for leakage power reduction in multicore chips.
Integr., 2019

Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation.
Integr., 2019

An orchestrated NoC prioritization mechanism for heterogeneous CPU-GPU systems.
Integr., 2019

Customized High Performance and Energy Efficient Communication Networks for AI Chips.
IEEE Access, 2019

Optimizing the Energy Efficiency of Power Supply in Heterogeneous Multicore Chips with Integrated Switched-Capacitor Converters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Compact Memory Structure based on 2T1R Against Single-Event Upset in RRAM Arrays.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Addressing Aging Issues in Heterogeneous Three-Dimensional Integrated Circuits.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Integrating low-resolution surveillance camera and smartphone inertial sensors for indoor positioning.
Proceedings of the IEEE/ION Position, Location and Navigation Symposium, 2018

2017
Machine Learning for Noise Sensor Placement and Full-Chip Voltage Emergency Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An outlier detection method and its application to multicore-chip power estimation.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
How secure is split manufacturing in preventing hardware trojan?
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

2015
A statistical methodology for noise sensor placement and full-chip voltage map generation.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2013
Placement optimization of power supply pads based on locality.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Optimized 3D Network-on-Chip Design Using Simulated Allocation.
ACM Trans. Design Autom. Electr. Syst., 2012

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Circuit reliability: From Physics to Architectures: Embedded tutorial paper.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
NoC frequency scaling with flexible-pipeline routers.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Thermal Impacts of Leakage Power in 2D/3D floorplanning.
J. Circuits Syst. Comput., 2010

Application-specific 3D Network-on-Chip design using simulated allocation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity.
IEEE Des. Test Comput., 2009

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2007
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007


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