Zwei-Mei Lee

According to our database, Zwei-Mei Lee authored at least 7 papers between 2003 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique.

Su-Hao Wu, Tsung-Kai Kao, Zwei-Mei Lee, Ping Chen, Jui-Yuan Tsai

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013

A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS.

Tieng Yi Choke, Hongke Zhang, Sam Chun-Geik Tan, W. Yang, Ying Chow Tan, Satyanarayana Reddy Karri, Yuan Sun, Dan Ping Li, Zwei-Mei Lee, Tianbao Gao, Weimin Shu, Osama Shana'a

IEEE J. Solid State Circuits, 2013

2011

A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application.

Chen-Yen Ho, Zwei-Mei Lee, Mu-Chen Huang, Sheng-Jui Huang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2007

A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration.

Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu

IEEE J. Solid State Circuits, 2007

2005

Correction to "A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration".

Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu

IEEE J. Solid State Circuits, 2005

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration.

Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu

IEEE J. Solid State Circuits, 2005

2003

A digital background calibration technique for pipelined analog-to-digital converters.

Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003