Äantas Kesten

Orcid: 0000-0001-6078-0713

According to our database1, Äantas Kesten authored at least 4 papers in 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Halfbex: RISC-V Narrow Data Path Optimization for Energy Reduction.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2025

A Nyquist-rate 128 GS/s 6-Bit 64x Time-Interleaved SAR ADC in 22nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Wideband Open-Loop Residue Amplifier for a 7-bit 10GS/s Two-Step Flash ADC in 22nm SOI CMOS Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Halfbex: A RISC-V Microarchitecture with Narrow Data Path for Improved Energy Efficiency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025


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