Friedel Gerfers
Orcid: 0000-0002-0520-1923
According to our database1,
Friedel Gerfers
authored at least 98 papers
between 2000 and 2024.
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Bibliography
2024
A Multiport Coaxial Interconnection for MTCA.4 Based High-Frequency Instrumentation Applications.
IEEE Trans. Instrum. Meas., 2024
2023
An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter.
IEEE J. Solid State Circuits, 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
25Gbps Automotive Ethernet ECU PCB: MDI Design Implementation and Insertion Loss Characterization.
Proceedings of the 9th International Conference on Vehicle Technology and Intelligent Transport Systems, 2023
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
A 12 GS/s RF-Sampler Employing Inductive Peaking with >57 dB |THD| and >49.3 dB SNDR in 22 nm FD-SOI CMOS.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A Digital Pre-Distortion Technique Canceling Code-and Voltage-Dependent Output Impedance Errors in Current-Steering DACs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 2023 Joint European Conference on Networks and Communications & 6G Summit, 2023
25Gbps Automotive Ethernet: System PHY Characterization of ESD Based EM Interferences.
Proceedings of the 28th IEEE International Conference on Emerging Technologies and Factory Automation, 2023
True Voltage-Mode NRZ VCSEL Transmitter enabling 60 Gbit/s at 0.37 pJ/bit in 22 nm FDSOI.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 2.41-μW/MHz, 437-PE/mm<sup>2</sup> CGRA in 22 nm FD-SOI With RISC-Like Code Generation.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023
2022
Sturdy-MASH Delta-Sigma Modulator with Improved Resolution Using Noise-coupling Multi-bit Quantizer.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
6G D-Band Receiver Model with High Spectral Efficiency Enabling Global System Optimization.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Beyond 10Gbps Electrical Automotive Ethernet Channel Insertion Loss Characterization.
Proceedings of the 2022 IEEE Intelligent Vehicles Symposium, 2022
A novel OFDM-based Radar and Communication System Design using Digital IQ-Modulation and 52 GS/s Direct-RF Data Converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A TI 12 GS/s Sampled Beam-Forming Receiver for a $2\times 2$ Antenna-Array with 69 dBc SFDR.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A Divider-less General PLL Lock Assist and Automatic Frequency Calibration System for Millimeter-Wave Sub-Sampling Phase-Locked Loops.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Characterization of Multi-Gigabit Automotive Ethernet Channel Radiated Emissions in Relation to ECU PCB Shield-Ground Implementations.
Proceedings of the 27th IEEE International Conference on Emerging Technologies and Factory Automation, 2022
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the Architecture of Computing Systems - 35th International Conference, 2022
2021
Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX<sup>®</sup>.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons.
IEEE Open J. Circuits Syst., 2021
A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks.
IEEE Open J. Circuits Syst., 2021
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2021
A Divider-less Automatic Frequency Calibration for Millimeter-Wave Sub-Sampling Phase-Locked Loops.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 56 GHz 19 fs RMS-Jitter Sub-Sampling Phase-Locked Loop for 112 Gbit/s Transceivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
Up to 30-Fold BER Improvement using a Data-Dependent FFE Switching Technique for 112Gbit/s PAM-4 VCSEL Based Links.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
A Transmission-Line-based Phase Shifter for High-Speed, Ultra-Low-Power N-PSK Transmitters.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Impedance Calibration Technique Canceling Process and Temperature Variation in Source Terminated DAC Drivers in 22nm FDSOI.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Optimized Zero Placement within Noise Coupling Transfer Functions for Oversampled ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
High Performance Electronic Design Education - from Technology towards High Frequency Chip Sets.
Proceedings of the IEEE Frontiers in Education Conference, 2019
A CMOS-Based Electrochemical DNA Hybridization Microarray for Diagnostic Applications with 109 Test Sites.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
2018
Digital-to-Analog Converters Using Frequency Interleaving: Mathematical Framework and Experimental Verification.
Circuits Syst. Signal Process., 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Analysis of Package Impedance Effects on the Linearity of Source Series Terminated DACs.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
AMDAC Common-Mode Shifting Technique enabling Power Consumption Reduction in Pipeline ADCs.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Noise and non-linearity analysis of a charge-injection-cell-based 10-bit 50-MS/s SAR-ADC.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Analysis and compensation technique canceling non-linear switch and package impedance effects of a 3.2GS/S TX-DAC.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A digital calibration technique canceling non-linear switch and package impedance effects of a 1.6GS/s TX-DAC in 28 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
High output power frequency doubler for digital PLLs in fully integrated 24 GHz CMOS radar systems.
Proceedings of the 17th IEEE International Conference on Ubiquitous Wireless Broadband, 2017
Proceedings of the IEEE EUROCON 2017 -17th International Conference on Smart Technologies, 2017
2016
Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2012
A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller.
IEEE J. Solid State Circuits, 2012
A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2008
IEEE J. Solid State Circuits, 2008
2007
On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
A continuous-time ΣΔ Modulator with reduced sensitivity to clock jitter through SCR feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speed.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A calibration method for current steering digital to analog converters in continuous time multi-bit sigma delta modulators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE J. Solid State Circuits, 2003
Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Influence of finite integrator gain bandwidth on continuous-time sigma delta modulators.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Compensation of the influence of finite gain-bandwidth on continuous-time sigma-delta modulators.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A clock jitter insensitive multibit DAC architecture for high-performance low-power continuous-time ΣΔ modulators.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback.
Proceedings of the ESSCIRC 2003, 2003
2002
A new kind of low-power multibit third order continuous-time lowpass Sigma-Delta modulator.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Figure of merit based design strategy for low-power continuous-time Sigma-Delta modulators.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000