Sebastian Linnhoff
According to our database1,
Sebastian Linnhoff authored at least 13 papers
between 2018 and 2026.
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Bibliography
2026
A 2×2 10GS/s TTD BF Receiver Utilizing Charge-Based Summation with 10.5GHz Bandwidth and SNDR/SFDR with 49.5dB/57.5dBc in 22nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
An 80 Gbit/s NRZ 100 Gbit/s PAM4 Highly-Efficient Voltage-Mode VCSEL-Driver in 22nm FDSOI CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 12 GS/s RF-Sampler Employing Inductive Peaking with >57 dB |THD| and >49.3 dB SNDR in 22 nm FD-SOI CMOS.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2018
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018