Aaron Stillmaker

Orcid: 0000-0002-7925-6177

According to our database1, Aaron Stillmaker authored at least 15 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Efficient and High-Performance Sparse Matrix-Vector Multiplication on a Many-Core Array.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

2020
Scalable energy-efficient parallel sorting on a fine-grained many-core processor array.
J. Parallel Distributed Comput., 2020

Hardware Implementation of HEVC Inverse Transform in 45nm CMOS.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019
Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" [Integr. VLSI J. 58. (2017) 74-81].
Integr., 2019

Impact of Coarse-Grained Power Gate Placement on a Fine-Grained System Design.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

2017
KiloCore: A Fine-Grained 1, 000-Processor Array for Task-Parallel Applications.
IEEE Micro, 2017

KiloCore: A 32-nm 1000-Processor Computational Array.
IEEE J. Solid State Circuits, 2017

Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm.
Integr., 2017

A configurable H.265-compatible motion estimation accelerator architecture for realtime 4K video encoding in 65 nm CMOS.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

2016
A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

KiloCore: A 32 nm 1000-processor array.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015
Area efficient backprojection computation with reduced floating-point word width for SAR image formation.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2012
Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012


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