Brent Bohnenstiehl

Orcid: 0000-0002-5149-9388

Affiliations:
  • University of California, Davis, CA, USA


According to our database1, Brent Bohnenstiehl authored at least 11 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2020
Scalable energy-efficient parallel sorting on a fine-grained many-core processor array.
J. Parallel Distributed Comput., 2020

2017
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs.
IEEE Trans. Very Large Scale Integr. Syst., 2017

KiloCore: A Fine-Grained 1, 000-Processor Array for Task-Parallel Applications.
IEEE Micro, 2017

KiloCore: A 32-nm 1000-Processor Computational Array.
IEEE J. Solid State Circuits, 2017

2016
A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

KiloCore: A 32 nm 1000-processor array.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015
Area efficient backprojection computation with reduced floating-point word width for SAR image formation.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

A software LDPC decoder implemented on a many-core array of programmable processors.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Scalable hardware-based power management for many-core systems.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
BAMSE: A balanced mapping space exploration algorithm for GALS-based manycore platforms.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013


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