Bevan M. Baas

According to our database1, Bevan M. Baas authored at least 54 papers between 2005 and 2019.

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Bibliography

2019
Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" [Integr. VLSI J. 58. (2017) 74-81].
Integr., 2019

2018
A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

KiloCore: A Fine-Grained 1, 000-Processor Array for Task-Parallel Applications.
IEEE Micro, 2017

KiloCore: A 32-nm 1000-Processor Computational Array.
J. Solid-State Circuits, 2017

Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm.
Integr., 2017

A configurable H.265-compatible motion estimation accelerator architecture for realtime 4K video encoding in 65 nm CMOS.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

2016
A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

KiloCore: A 32 nm 1000-processor array.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015
Area efficient backprojection computation with reduced floating-point word width for SAR image formation.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

A software LDPC decoder implemented on a many-core array of programmable processors.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks.
IEEE Trans. VLSI Syst., 2014

Achieving High-Performance On-Chip Networks With Shared-Buffer Routers.
IEEE Trans. VLSI Syst., 2014

Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Hybrid floating-point modules with low area overhead on a fine-grained processing core.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

Scalable hardware-based power management for many-core systems.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization.
VLSI Design, 2013

Parallel AES Encryption Engines for Many-Core Processor Arrays.
IEEE Trans. Computers, 2013

2012
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

2011
A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System.
IEEE Trans. Circuits Syst. Video Techn., 2011

Low power LDPC decoder with efficient stopping scheme for undecodable blocks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

RoShaQ: High-performance on-chip router with shared queues.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

A reduced routing network architecture for partial parallel LDPC decoders.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

A high-performance area-efficient AES cipher on a many-core platform.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders.
Signal Processing Systems, 2010

A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2010

A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders.
IEEE Trans. on Circuits and Systems, 2010

A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Circuit modeling for practical many-core architecture design exploration.
Proceedings of the 47th Design Automation Conference, 2010

2009
High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2009

A 167-Processor Computational Platform in 65 nm CMOS.
J. Solid-State Circuits, 2009

A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Multi-Split-Row Threshold Decoding Implementations for LDPC Codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

The Design of a Reconfigurable Continuous-flow Mixed-radix FFT Processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes.
Proceedings of IEEE International Conference on Communications, 2009

2008
Architecture and Evaluation of an Asynchronous Array of Simple Processors.
Signal Processing Systems, 2008

AsAP: An Asynchronous Array of Simple Processors.
J. Solid-State Circuits, 2008

A low-area interconnect architecture for chip multiprocessors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Dynamic voltage and frequency scaling circuits with two supply voltages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A high-performance parallel CAVLC encoder on a fine-grained many-core system.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains.
IEEE Trans. VLSI Syst., 2007

AsAP: A Fine-Grained Many-Core Platform for DSP Applications.
IEEE Micro, 2007

A Shared Memory Module for Asynchronous Arrays of Processors.
EURASIP J. Emb. Sys., 2007

High-Throughput LDPC Decoders Using A Multiple Split-Row Method.
Proceedings of the IEEE International Conference on Acoustics, 2007

2006
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005
A generalized cached-FFT algorithm.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005


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