Abderrahim Doumar

According to our database, Abderrahim Doumar authored at least 14 papers between 1999 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2011

Video acquisition between USB 2.0 CMOS camera and embedded FPGA system.

Abderrazak Abdaoui, K. Gurram, M. Singh, A. Errandani, Eric Châtelet, Abderrahim Doumar, Tarek M. El-Fouly

Proceedings of the 5th International Conference on Signal Processing and Communication Systems, 2011

Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems.

Farid Lahrach, Abderrahim Doumar, Eric Châtelet

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Fault tolerance of SRAM-based FPGA via configuration frames.

Farid Lahrach, Abderrahim Doumar, Eric Châtelet

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA.

Farid Lahrach, Abderrahim Doumar, Eric Châtelet, Abderrazek Abdaoui

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks.

Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Châtelet

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2007

Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.

Abderrahim Doumar, Kentaroh Katoh, Hideo Ito

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2005

Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.

Kentaroh Katoh, Abderrahim Doumar, Hideo Ito

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2003

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey.

Abderrahim Doumar, Hideo Ito

IEEE Trans. Very Large Scale Integr. Syst., 2003

2000

Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources.

Abderrahim Doumar, Hideo Ito

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Testing approach within FPGA-based fault tolerant systems.

Abderrahim Doumar, Hideo Ito

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

An Automatic Testing and Diagnosis for FPGAs.

Abderrahim Doumar, Hideo Ito

Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

Design of an automatic testing for FPGAs.

Abderrahim Doumar, Toshiaki Ohmameuda, Hideo Ito

Proceedings of the 4th European Test Workshop, 1999

Defect and Fault Tolerance FPGAs by Shifting the Configuration Data.

Abderrahim Doumar, Satoshi Kaneko, Hideo Ito

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Testing the Logic Cells and Interconnect Resources for FPGAs.

Abderrahim Doumar, Hideo Ito

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999